MPMC2 has been replaced by MPMC v3.00.a (and later versions), which is integrated into EDK (version 9.2 and later).
The latest version of MPMC is strongly recommended for all new designs.
Limited support is available for MPMC2.
Please refer to Answer Record #29564 for migration details and support.
The second generation Multi Port Memory Controller (MPMC2) provides an enhanced set of features and capabilities for high performance system topologies.
MPMC2 builds upon the technology introduced in MPMC1 as part of the Gigabit System Reference Design (GSRD). By allowing parallel transactions across ports, MPMC2 reduces bus arbitration and enhances system level traffic flow. Additionally, tightly coupled DMA engines provide high bandwidth access to memory and low resource utilization. The highly configurable nature of MPMC2 provides a significant advantage compared to MPMC1's fixed solution.
The flexibility and scalability of MPMC2 supports multiple memory standards in different data widths. The highly ergonomic Graphical User Interface (GUI) allows engineers to rapidly customize MPMC2's features including:
- Number of ports (Scalable from 1 to 8)
- Type of memory (e.g. DDR, DDR2, user defined)
- Width of memory (8, 16, 32 or 64-bit)
- Various Port Interface Modules (Processor Interfaces, DMA engines, Standalone, etc)
- Memory device part number
- Arbitration methodology
- Selectable pipeline stages for frequency matching
Example system topologies using MPMC
MPMC2 extends the range of possible solutions by providing designers additional design capability for higher performance and/or advanced system topologies. System topologies can be built utilizing different types of Port Interface Modules (PIMs) on a per-port basis.
These seven types of PIMs are presently supported:
- IBM™ CoreConnect™ Processor Local Bus (PLB PIM)
- IBM CoreConnect On-chip Peripheral Bus (OPB PIM)
- PPC405 Instruction Side Processor Local Bus (ISPLB PIM)
- PPC405 Data Side Processor Local Bus (DSPLB PIM)
- Communication Direct Memory Access Controller (CDMAC PIM)
- Native Port Interface (NPI PIM)
- Xilinx MicroBlaze™ CacheLink (XCL PIM)
The four pictures below represent a small sampling of possible system topologies: 
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