Xilinx supports Full System Hardware Evaluation of the DVB-S.2 FEC Encoder LogiCORE™ IP core.

The evaluation license keys for this core will enable you to parameterize, generate and instantiate this IP in your design. It will also allow you to perform functional and timing simulation, generate a bitstream, and download and configure your design in hardware. The resulting IP will be fully functional in the FPGA for 2-3 hours, after which it will cease to function. To restore the evaluation core's operation in your design, simply reconfigure the FPGA with the bitstream.

To perform a Full System Hardware Evaluation:

1. Make sure you have satisfied the requirements.
2. Generate a Full System Hardware Evaluation License Key.
   • The license will be generated and emailed to you automatically. Install the license as directed by the email instructions.
3. Follow the general instructions below on Generating the Core.
4. To perform an in-depth evaluation in hardware in your own design:
• Instantiate the core in your own design, place and route the design using ISE, then generate a bitstream and use it to program an appropriate FPGA device.

• Start the CORE Generator™ using either of the following methods:
  • From ISE: Select Projects -> New Source -> IP (Coregen and Architecture Wizard)
  • From Windows: Select Programs -> Xilinx -> Accessories -> CORE Generator
• The DVB-S.2 FEC Encoder core is located in the Digital Signal Processing / Error Correction folder in the IP catalog section of the CORE Generator window.

Please review the Master Release Notes Guide for Xilinx IP Cores