Xilinx provides two ways to evaluate the Fibre Channel (FC) LogiCORE™ IP core: Simulation Only, and Full System Hardware Evaluation.

• Simulation Only Evaluation allows you to customize the core through a CORE Generator™ customization GUI and generate a UNISIM library-based structural model for functional simulation.
• A Full System Hardware Evaluation version of the FC core allows you to do everything you can do with the Fully Licensed IP core, including configure place and route, simulate, estimate timing and program a Xilinx FPGA device.

• Please refer to the Xilinx Fibre Channel Solution Offerings and System Requirements Schedule for details on System Requirements for the Fibre Channel core.

To perform a Simulation Only Evaluation:

• Make sure you have satisfied the requirements listed in the section above.
• Follow the Installation Instructions in the Master IP Release Note Guide to install the required ISE® software and IP Update.
• Follow the General Instructions to access and evaluate the core.

To perform a Full System Hardware Evaluation: The procedures are the same as for the Simulation Only Evaluation, except that you must additionally request and install a Full System Hardware Evaluation license key. This will allow you to generate a bitstream that you can use to program a Xilinx FPGA and evaluate the core in hardware for a limited amount of time.

1. Make sure you have satisfied the Requirements.
2. Generate a Full System Hardware Evaluation License Key.
• The license will be generated and emailed to you automatically. Install the license as directed by the email instructions.
3. Follow the general instructions below to load the CORE Generator IP customization GUI for this core and generate the core.
4. To familiarize yourself with the ISE design flow,
   • Process the Example Design delivered with the core through ISE following the Quick Start instructions in the Getting Started Guide .
5. To perform an in-depth evaluation in hardware in your own design:
   • Instantiate the core in your own design, place and route the design using ISE, then generate a bitstream and use it to program an appropriate FPGA device.

• Start up the CORE Generator using either of the following two methods:
  • From ISE: Select Projects -> New Source -> IP (Coregen and Architecture Wizard)
  • From Windows: Select Programs -> Xilinx ISE 10.1 -> Accessories -> CORE Generator
• The Fibre Channel Pt. to Pt. core is located in the Storage, NAS and SAN folder in the IP catalog section of the CORE Generator window.
  • Double click on the core to call up the customization GUI, select your desired parameters, and click the "Finish" button to generate the core.

Refer to the Example Design Quick Start chapter of the Getting Started Guide for more detailed instructions on evaluating the core.

You can learn more about the Xilinx Fibre Channel core by visiting the Fibre Channel Pt. to Pt. product page.

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