Xilinx provides two ways to evaluate the Generic Framing Procedure (GFP) LogiCORE™ IP core: Simulation Only, and Full System Hardware Evaluation.

• Simulation Only Evaluation allows you to customize the core through a CORE Generator™ software customization GUI and generate a UniSim-based model for functional simulation.
• Full System Hardware Evaluation allows you to do everything you can do with the Fully Licensed IP core, including configure place and route, simulate, estimate timing and program a Xilinx FPGA device.

Install these updates if you have not already done so:

1. Install the required updates as specified in the Software Requirements section of the GFP Offerings and System Requirements in one of the following ways:

• Run WebUpdate from the ISE Project Navigator Help menu, or CORE Generator software Tools menu,
• Download the indicated updates from the Xilinx Download Center and run the standalone installer

2. The required ISE® Service Pack is automatically installed with the selected IP Update when using either method.
3. Review the Critical Information link for the IP Update on Download Center for Installation instructions and Release Note information on What's New, Bugs Fixed and Known Issues.

(NOTE: You must be registered on Xilinx.com to access these updates.)

To perform a Simulation Only Evaluation:

1. Make sure you have installed the required software as specified in the requirements section to ensure that you have the required software and IP core version. The Simulation Evaluation license key is shipped with the core by default.
2. Follow the general instructions below on Generating the Core.
3. Integrate the core into your design and perform a functional simulation. See the Getting Started Guide for more details.

To perform a Full System Hardware Evaluation:

1. Make sure you have satisfied the requirements.
2. Generate a Full System Hardware Evaluation License Key.
   • The key will be generated and emailed to you automatically. Install the license as directed by the email instructions.
3. Follow the general instructions below on Generating the Core.
4. To familiarize yourself with the ISE design flow,
• Process the Example Design delivered with the core through ISE following the Quick Start instructions in the Getting Started Guide.
5. To perform an in-depth evaluation in hardware in your own design:
• Instantiate the core in your own design, place and route the design using ISE, then generate a bitstream and use it to program an appropriate FPGA device.

• Start the CORE Generator using either of the following methods:
  • From ISE: Select Projects -> New Source -> IP (Coregen and Architecture Wizard)
  • From Windows: Select All Programs -> Xilinx 10.1 Design Suite -> ISE -> Accessories -> CORE Generator
• The GFP core is located in the Communication and Networking folder in the IP catalog section of the CORE Generator window.

Refer to the Example Design Quick Start chapter of the Getting Started Guide for more detailed instructions on evaluating the core.

Please refer to the Master Release Notes Guide for Xilinx IP Cores for the latest information on the Release Notes and Known Issues for this core.