Xilinx provides two ways to evaluate the LogiCORE™ IP MOST® NIC IP core: Simulation Only and Full System Hardware Evaluation.

• Simulation Only Evaluation allows you to customize the core through a CORE Generator™ customization GUI and generate a Unisim Library-based structural model for functional simulation.
• Full System Hardware Evaluation version of the core allows you to do everything you can do with the Fully Licensed IP core, including configure, place and route, simulate, estimate timing and generate a bitstream that you can use to program a Xilinx FPGA device. The core will function in the programmed device for approximately 8 hours, depending on your design clock speed.

Please refer to the Xilinx MOST NIC License, Offerings and System Requirements for a summary of offerings and required software and IP Update levels.

(NOTE: You must be registered on Xilinx.com to access these updates.)

To perform a Simulation Only Evaluation:

1. Make sure you have satisfied the above requirements for accessing this core. This will ensure that you have the required software and IP core version. The Simulation Eval license key is shipped with the core by default.
2. Install the required updates following these instructions (Automatic or Manual Method): ISE® CORE Generator IP Updates - Installation Instructions to install the archive onto your Xilinx ISE 10.1.2 software installation
3. Follow the instructions below on Generating the Core

To perform a Full System Hardware Evaluation:

1. Before you can acquire a hardware evaluation license for the core, you must become a member of the MOST Cooperation.
2. Install the required updates following these instructions (Automatic or Manual Method): ISE CORE Generator IP Updates - Installation Instructions to install the archive onto your Xilinx ISE 10.1.2 software installation
3. Use the Evaluation License Key Generation Form to Generate a Full System Hardware Evaluation License Key and follow the emailed instructions to install the key on your machine.
4. Follow the general instructions below on Generating the Core.

1. Start up the CORE Generator using either of the following methods:
   • From ISE: Select Projects -> New Source -> IP (Coregen and Architecture Wizard)
   • From Windows: Select Programs -> Xilinx ISE 10.1.2 -> Accessories -> CORE Generator
2. To access the core:
   • Double-click on the Automotive & Industrial folder in the left hand panel of the CORE Generator GUI
   • Double-click on the Automotive folder, and click on MOST. The selected Core will appear in the right hand panel of the CORE Generator GUI.
   • Double-click on the MOST entry in the left hand catalog panel, or single click on the Customize link in the right hand panel to call up the MOST NIC IP customization GUI.
3. Select the desired options for the core, clicking on Next to proceed to the next panel. When all options have been selected, click on the Finish button.
4. The following support files will be generated in your CORE Generator project directory:
   • .NGC implementation netlist
   • .VEO or .VHO file (Verilog or VHDL instantiation template)
   • .VHD or .V structural Unisim simuilation model
   • .XCO log file
5. The following support files are written to a subdirectory named <user_specified_corename> located within the project directory:
   • Release Notes: <user_corename>_release_notes.txt
   • Supporting documentation
   • Subdirectories containing example wrapper files
   • Scripts to run the core through the ISE tools (NgdBuild, Map, PAR) and to simulate the core using the Mentor ModelSIM simulator

Follow the instructions in the Getting Started Guide to complete your evaluation.

You can learn more about the Xilinx MOST NIC core by visiting the MOST NIC product page.