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Embedded Processing Peripheral IP Cores

Related Information
MicroBlaze Soft Processor
PowerPC 440
Embedded Processor
PowerPC 405
Embedded Processor
EDK Documentation
IP Center

The following cores are included with the EDK.  Each one works directly in Xilinx Platform Studio with the MicroBlaze™ soft processor as well as the PowerPC® processors.

Processor IP Cores
Description  
MicroBlaze Processor (PDF)  
PowerPC 440 Processor: Virtex®-5 FPGAs (PDF)  
PowerPC 405 Processor: Virtex-4 FPGAs (PDF)  
PowerPC 405 Processor: Virtex-II Pro FPGAs (PDF)  
Bus / Bridge IP Cores
Description  
PowerPC Device Control Register Bus (PDF) 
Data Side OnChip Memory Controller (PDF)  
Fast Simplex Link Bus (PDF) 
Instruction Side OnChip Memory Controller (PDF) 
Local Memory Bus (PDF) 
MultiChannel to PLBv46 Interface (PDF) 
Processor Local Bus (PLBv46) (PDF) 
PLBv46 to DCR Bridge (PDF) 
PLBv46 to User IP Master Burst Core (PDF) 
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Peripheral IP Cores
Description  
XPS Controller Area Network (PDF) DO-DI-CAN*
XPS Central DMA (PDF) 
XPS Delta-Sigma ADC (PDF) 
XPS Delta-Sigma DAC (PDF) 
XPS External Peripheral Controller (PDF) 
XPS EthernetLite Controller (PDF) 
XPS FlexRay™ Controller (PDF) DO-DI-FLEXRAY*
XPS General Purpose I/O (PDF) 
XPS Hardware ICAP Controller (PDF) 
XPS I2C Controller (PDF) 
XPS Interrupt Controller (PDF) 
XPS LocalLink FIFO (PDF) 
XPS LocalLink TriMode Ethernet MAC (PDF) DO-DI-TEMAC*
XPS Mailbox (PDF) 
XPS Mutex (PDF) 
XPS SPI Controller (PDF) 
XPS System Ace™ Interface Controller (PDF)  
XPS System Monitor Interface (PDF) 
XPS Timebase / Watchdog Timer (PDF) 
XPS Counter / Timer (PDF) 
XPS 16550 UART (PDF) 
XPS UARTLite (PDF) 
XPS USB2 Endpoint Controller (PDF) DO-DI-USB2-DEVICE*
PLBv46 PCI Full Bridge (PDF) DO-DI-PLBV46-PCI*
PLBv46 PCIe® Bridge (PDF)  
DMA Channelized Scatter / Gather Controller (PDF) 
DCR Interrupt Controller (PDF) 
Fixed Interval Timer (PDF) 
MII to RMII Interface (PDF) 
*Part number for separate license.
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Infrastructure IP Cores
Description  
Clock Generator Module (PDF) 
Floating Point interface for Virtex-5 FPGAs (PDF)  
Floating Point interface for Virtex-4 FPGAs (PDF)  
JTAG Controller for PPC (PDF) 
Phase Lock Loop Module (PDF) 
Processor Reset Controller (PDF) 
Bus Splitter Utility (PDF) 
Flip-Flop Utility (PDF)  
Vector to Bit Reduction Utility (PDF) 
Vector Logic Utility (PDF) 
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Memory / Memory Controller IP Cores
Description  
MultiPort Memory Controller (PDF) 
PowerPC 440 DDR2 Memory Controller (PDF)  
PowerPC D-Side OCM BRAM Controller (PDF)  
PowerPC I-Side OCM BRAM Controller (PDF)  
MicroBlaze LMB BRAM Controller (PDF) 
MultiChannel OPB DDR2 Controller (PDF) 
MultiChannel OPB DDR Controller (PDF) 
MultiChannel OPB Ext. Memory Controller (PDF) 
MultiChannel OPB SDRAM Controller (PDF) 
XPS BRAM Controller (PDF) 
XPS MultiChannel Ext. Memory Controller (PDF) 
Debug IP Cores
Description  
ChipScope ILA Core (PDF) 
ChipScope PLBv46 IBA Core (PDF) 
ChipScope VIO Core (PDF) 
MicroBlaze Debug Module (PDF) 
Xilinx MicroBlaze Trace Core (PDF) 
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