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The Vivado® Design Suite shatters the RTL design productivity plateau by providing the industry’s first plug-and-play IP integration design environment, with its IP Integrator feature.

Vivado IP Integrator provides a graphical and Tcl-based, correct-by-construction design development flow. It provides a device and platform aware, interactive environment that supports intelligent auto-connection of key IP interfaces, one-click IP subsystem generation, real-time DRCs, and interface change propagation, combined with a powerful debug capability.

Designers work at the “interface” and not “signal” level of abstraction when making connections between IP, greatly increasing productivity.  Often times this is using industry standard AXI4 interfaces, but dozens of other interfaces are also supported by IP integrator.

Working at the interface level, design teams can rapidly assemble complex systems that leverages IP created with Vivado HLS, System Generator, Xilinx SmartCore™ and LogiCORE™ IP, Alliance Member IP as well as your own IP. By leveraging the combination of Vivado IPI and HLS customers are saving up to 15X in development costs versus an RTL approach.

Vivado IP Integrator benefits include:

  • Tight integration within the Vivado Integrated Design Environment
    • Seamless inclusion of IP Integrator hierarchical subsystems into the overall design
    • Rapid capture and packaging of IP Integrator designs for reuse
    • Support for both graphical and Tcl-based design flows design
    • Rapid simulation and cross-probing between multiple design views
  • Support for all design domains
    • Support for processor or processor-less designs
    • Integration of algorithmic (Vivado HLS and System Generator) and RTL-level IP
    • Combination of DSP, video, analog, embedded, connectivity, and logic
  • Focused on Designer Productivity
    • DRCs on complex interface level connections during design assembly
    • Recognition and correction of common design errors
    • Automatic IP parameter propagation to interconnected IP
    • System-level optimizations
    • Automated designer assistance

C-based IP Generation with Vivado High-Level & Synthesis Model-based DSP Design Integration

As the leading provider of Electronic System Level Design tools for All Programmable solutions, Vivado Design Suite System Edition provides Vivado High-Level Synthesis for C, C++ and SystemC, and MATLAB™/Simulink™ based System Generator for DSP. These solutions enable high-level IP specifications to be directly synthesized into VHDL and Verilog accelerating IP verification over 100X and RTL creation by up to 4X. The highly integrated tools can be used individually or in combination with the result being reusable IP for use in the Vivado Design Suite.

Developer Zone

For FPGA designers looking to shorten design time and ensure scalability and re-use, Xilinx provides a comprehensive suite of solutions ranging from C-based design abstractions to IP plug-and-play to address bottlenecks in hardware development, system-level integration, and implementation.

software-tile
Xilinx's software development environments and embedded platforms offer a comprehensive set of familiar and powerful tools, libraries and methodologies.
Acceleration Zone
Xilinx UltraScale™ and UltraScale+ FPGAs are empowering hardware and application developers in many of the world’s largest and most innovative cloud computing services.
hardware-tile
Xilinx All Programmable devices take conventional programmable logic to an era of integrated programmable systems to capitalize on the benefit of System Integration.
revision-tile
Xilinx provides machine learning solutions including the development stacks and hardware platforms for deploying advanced and efficient neural networks, algorithms and applications.
system-tile
Xilinx works closely with world class partners like The Mathworks™ and National Instruments™ to enable rapid system development with unrivaled levels of system performance.
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