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The following is a checklist that was designed to assist PCB and system designers in completing a PCB without forgetting any critical SI-related details.
Layers
Bypassing
Simultaneously Switching Outputs (SSO)
Signal Paths (PCB traces and terminations)
Power Supply and Power Management
Design for Debug
At least one Ground Plane present
Every board must have at least one continuous ground plane. This is required for three main reasons. First, it provides a low-impedance power system. Second, it makes the connection of low-impedance vias to device GND pins very convenient. Third, it provides a path for return currents. All of these are very important in keeping ground noise at a minimum, both on the board and in
the devices.
Dedicated plane for VCCo
Though not necessary, board layout is greatly simplified when a continuous, dedicated or semi-dedicated VCCo plane is included. It makes routing connections to power pins and bypass capacitors more accessible and provides a low-impedance path for return currents.
Every signal trace is within one signal layer of a continuous reference plane
Every trace in the stackup should either be adjacent to a reference (power or ground) plane, or only separated from the closest reference plane by one signal layer. This ensures that return currents always travel as closely as possible to their corresponding trace. Adjacent signal layers should run in a perpendicular directions, such that vertical and horizontal layers alternate.
This limits crosstalk between signal traces of adjacent layers. To maintain constant impedance from layer to layer, the trace widths should be adjusted for each layer, as in Figure 1 below. See page 3 of XAPP231 for information on calculating the characteristic impedance of a PCB trace based on its dimensions, or use a field solver. Continuity of the reference plane is of utmost importance. Signal traces should never cross discontinuities in its associated reference plane, such as a large hole, slot, or break in the plane.
Fig. 1
High-frequency capacitor within 1 to 2 cm of each VCC pin
High-frequency bypass capacitors are the smallest capacitors in the bypassing network. There should be at least one high-frequency capacitor on every VCC/GND pair, and it should be mounted within 1 to 2 centimeters of the VCC pin it is bypassing. The best location for these capacitors is on the underside of the PCB, directly under the FPGA.
Capacitor vias should never be shared. Each capacitor requires at least 2 vias -- one for its ground connection and one for its vcc connection. Vias should descend directly to the power and ground planes (traces should not be used to connect bypass capacitors to the power pins they are servicing).
The total capacitance of all high-frequency capacitors must equal at least 25 times the equivalent switched capacitance ( C=P/(FV2) for VCCint, C=CLOAD*N for VCCio). For greater noise immunity, a factor of 50 or 100 should be used instead of 25. When one capacitor per VCC/GND pin is used, this calculation usually gives rise to values in the range of 0.1µF or 0.01µF.
Smaller values of 0.0047µF and 0.0033 µF should be used in addition.
All high-frequency capacitors should be low ESR ceramic chip type. In every case, the smallest package for a given capacitor value should be used. See page 2 of XAPP158 for more information on choosing capacitor size and characteristics. See capacitor vendors' websites for specific information on capacitor characteristics (http://www.avxcorp.com/, http://www.tdk.com/).
Mid-frequency capacitors within 8cm of VCC pins
Mid-frequency bypass capacitors are capacitors in the range of 4.7µF to 47µF, and should be of low ESR, low inductance type. Tantalum capacitors are ideal, though aluminum electrolytic type may also be used. There should be at least one for every 3000 slices (two for V400? four for V1000, 7 for V2000E).
Low-frequency capacitors anywhere on PCB
Low-frequency bypass capacitors for board bypassing are in the range of 47 µF to 4700 µF. These can be of any type and located anywhere on the board.
Bypass capacitor on each Vref pin
Because of their high input impedance, Vref pins are succeptible to noise coupled in from surrounding signals. For this reason, every Vref pin needs a local bypass capacitor of value from 0.01µF to 0.1µF. Noise from the power supply is not a concern, so use of inductors or ferrite beads is not appropriate here.
SSO guidelines have been checked
See the datasheet for SSO guidelines. Multiply the number of effective VCC/GND pairs in your device (value in a chart, by device/package combination), by the SSO guideline number (value in a chart, by IO standard), to find out the total number of outputs that may safely be driven. This is easiest to compute on a bank by bank basis. Exceeding these guidelines can lead
to serious Ground Bounce problems.
Each trace has constant impedance
Every signal trace should maintain the same impedance no matter where it goes. Signal traces may be of any practical impedance value (40 ohms to 100 ohms is common). The same design may have signal traces with a variety of different impedance values. However, a single trace should not change impedance values over its length. For example, if a trace starts on one board
layer and switches to another layer, the designer must ensure that the trace on the second layer has the same impedance as the first. If the layers are different distances from their respective reference planes, the widths of the signal traces should be adjusted accordingly. In general, if the distance to the reference plane is increased, the trace width must also be increased in
order to maintain the same impedance. This can be seen in Figure 1 above.
Traces longer than Tr/6 have been simulated
The ratio of signal rise/fall time to trace length can determine whether or not transmission-line effects will occur. In general, long traces with fast rise/fall times exhibit transmission-line effects. If the time it takes a signal to propagate down the length of the trace is more than 1/6 of the signal rise/fall time, transmission-line effects are likely, and the signal
path must be simulated. This can be perfomed in an IBIS or SPICE simulator. For more information on transmission-line effects and simulation, see the text references at the end of this document.
If ringing or overshoot is observed, add termination or change IO standard
If a transmission line is simulated and it exhibits ringing or overshoot, this means there is an unacceptable amount of signal reflection present. Signal reflection occurrs when a signal wave encounters an impedance discontinuity. To repair the ringing or overshoot, the impedance discontinuity must be eliminated. This can be accomplished through one of three methods:
add resistive termination to the PCB (in series or parallel), change the SelectIO standard to one with a lower current drive, or use XCITE DCI (in Virtex-2). For more information on termination, see the text references at the end of this document.
Extra attention has been paid to clock signals (GCLK, CCLK, TCK etc)
Clock signals require special attention for two reasons. First, it is critical that their timing not be marginalized by noise - this can lead to false clocking of data. Second, clock signals often run at a higher frequency than data, and so can be more troublesome as noise sources. Clock traces and their drivers should ALWAYS be carefully simulated prior to PCB fabrication.
Long, closely-spaced parallel traces have been analyzed for crosstalk
Attention should be paid to any traces which run in parallel for long distances. Any suspicious traces should be simulated using a PCB crosstalk simulation tool to determine if they will cause problems. If crosstalk is confirmed to be a problem, it may be managed by separating the traces or decreasing their distance from the associated reference plane (decrease dielectric
thickness).
Total FPGA power estimated with Power Estimator or XPower
The Power Estimator or XPower should be used to determine the approximate power the FPGA will require. The Power Estimator requires design data generated by MAP (CLB utilization, Flops, IO standard, BlockRAM usage). XPower is part of the design flow. These provide a guideline for power supply requirements and also are essential for thermal planning.
Power supply satisfies POR monotonicity and ramp rate requirements
The power supplies should rise from less than 0.1 Vdc to the minimum DC operating condition voltage level in less than 50 milliseconds, and not faster than 1 millisecond. The rise should not be inhibited by a current trip, or current foldback. Current limit behavior is acceptable based on the "Power-On Ramp Up Current Requirement" specification from the data sheet. The
voltage rise vs. time should be roughly monotonic. Dwelling at a voltage, or having a 'plateau', while acceptable power supply behavior, should be avoided. Having the voltage go up over the minimum operating voltage and then drop below this value will result in incorrect power on behavior. When the power supply voltage falls below the absolute minimum operating voltage when turned
off, it shall not rise immediately back to the nominal operating voltage when turned on without first discharging back down below 0.1 Vdc. A resistor may be required to bleed off charge on the filter and bypass capacitors to insure this condition is met.
Power supply satisfies POR minimum current requirement
Aside from meeting the dynamic power requirements determined using the Power Estimator, the power supply must also be capable of supplying the minimum specified startup current. This is given in the datasheet.
Die temperature predicted by TJ = TA + P*QJA is less than max allowable
Using the power figure derived from the Power Estimator, information about the device package, and the maximum ambient temperature in the operating environment, the die temperature should be determined. If this figure is higher than the maximum allowable temperature for the device's temperature grade (C = Commercial: 0?C - 80?C, I = Industrial: -40?C - 100?C), a change
must be made to the design (lower ambient temperature, addition of a heatsink, change of package, reduced clock frequency or reduced device utilization). For more information on thermal planning and management, see page 1 of XAPP158 and chapter 8 of the 2000 Databook.
JTAG header included on board (connected to JTAG pins of device)
Every PCB should have easy access to the FPGA's JTAG pins. This allows for debugging if necessary in the final system. The best method is to route the TCK, TMS, TDI and TDO signals to a four-pin header on the PCB. This is especially critical with BG and FG packages where there is limited access to device pins. The designer may also wish to provide ground and VCC pins
in the header for convenience (six pins).
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