As IO switching frequencies have increased and voltage levels have decreased, accurate analog simulation of IOs has become an essential part of modern high-speed digital system design. By accurately simulating the IO buffers, termination and circuit board traces, designers can significantly shorten their time-to-market of new designs. By identifying signal integrity related issues at the beginning of the design cycle, the number of board fixes is decreased.

Traditionally SPICE analysis has been used extensively in areas like IC design, where a high level of accuracy is required. However in the PCB and systems domain, there are several disadvantages to the SPICE method, both for the user and the device vendor.

Since SPICE simulations model a circuit at transistor level, it is necessary for the SPICE models to contain detailed information about the circuit and process parameters. For most IC vendors, this type of information is regarded as proprietary and there is usually a great deal of resistance against making the models public.

Although SPICE simulation accuracy is typically very good, a big limitation with any simulation method is simulation speed. Simulation speeds are particularly slow for transient simulation analysis, which is most often used when evaluating signal integrity performance. SPICE simulation has a further disadvantage in that not all SPICE simulators are fully compatible. Oftentimes, default simulator options are not the same in different SPICE simulators. As there are some very powerful options which control accuracy, convergence and the algorithm type, any options which are not consistent may give rise to poor correlation in simulation results across different simulators. Also, because of the different variants of SPICE, these models are often incompatible between simulators, thus models must be extracted for a specific simulator.

An alternative to Spice simulation is IBIS (I/O Buffer Information Specification). Intel originally developed IBIS with the aim of giving customers access to accurate IO buffer models while protecting their intellectual property. The IBIS specification is now maintained by the EIA/IBIS Open Forum, which has members from a large number of IC and EDA vendors.

The core of the IBIS model consists of a table of current versus voltage and timing information. This is very attractive to the IC vendor as the IO internal circuit is treated as a black box. This way, transistor level information about the circuit and process details are not revealed.

Using IBIS models has a great advantage to the user in that simulation speed is significantly increased over SPICE, while accuracy is only slightly decreased. Non-convergence, which can be a problem with SPICE models and simulators, is eliminated in IBIS simulation. Virtually all EDA vendors presently support IBIS models and ease of use of these IBIS simulators is generally very good. IBIS models for most devices are freely available over the Internet making it easy to simulate several different manufacturers devices on the same board.

Xilinx provides IBIS models for all current products, which can be easily downloaded from our web site. Xilinx SPICE models are only available upon completion of an NDA (Non-Disclosure Agreement) and application evaluation process, and therefore it is recommended that IBIS models be used wherever possible.

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