MicroBlaze Processor Architecture

The award winning MicroBlaze™ soft processor is a 32-bit Harvard RISC architecture, optimized for the Xilinx FPGA families. The the basic MicroBlaze architecture is consists of 32 general-purpose registers, an Arithmetic Logic Unit (ALU), a shift unit, and two levels of interrupt. This basic design can then be configured with more advanced features such as: memory management unit (MMU), barrel shifter, memory management/memory protection unit, floating-point unit (FPU), caches, exception handling, debug logic, and others. This flexibility allows the user to balance the required performance of the target application against the logic area cost of the soft processor.

Figure 1

MicroBlaze Embedded System

The general purpose processor interface conforms to the CoreConnect™ Processor Local Bus (PLB) and On-Chip Peripheral Bus (OPB) standard.
The Fast Simplex Link (FSL) is a simple, yet powerful, point-to-point interface that connect user-developed co-processors to the MicroBlaze pipeline.

Configurable Features

• Memory Management Unit (MMU)
  • Full MMU with Virtual Memory supported by Linux 2.6
  • MPU mode for region protection for secure RTOS applications
• Floating Point Unit
  • IEEE 754 compatible
  • Single precision
  • For details, see MicroBlaze FPU
• Hardware Exception Support
  • Unaligned access
  • Illegal instruction
  • Data bus error
  • Instruction bus error
  • Divide-by-zero
  • Floating point exceptions
• Fast Simplex Link Co-processor Interface
  • Direct access to the general purpose registers for hardware acceleration
  • Up to 8 dedicated 32-bit input ports
  • Up to 8 dedicated 32-bit output ports
• Instruction and Data Caches
  • Uses on-chip block RAM primitives
  • Configurable size 2kB - 64kB
  • Configurable micro-cache (using distributed RAM)  size 64B – 1024B
  • Direct mapped write-through operation
  • 4 or 8 word cache lines
• System Interface
  • Different combinations of PLBv46, OPB, LMB and FSL for flexible system design
    • On-chip Peripheral Bus (OPB) for interfacing to peripherals
    • Local Memory Bus (LMB) for fast local access memory
    • Fast Simplex Link (FSL) for interfacing to co-processors
• Barrel Shifter
  • 1 cycle operation
• Hardware Integer Divide
  • 32 cycle operation
• Hardware Multiply
  • 1 cycle operation
  • MUL64 operation
• Debug Logic
  • JTAG control via a debug support core
  • Up to 8 hardware break points
  • Up to 4 read address watch points
  • Up to 4 write address watch points
• Instruction Set Extensions
  • Pattern Compare Instructions
  • Machine Status Register Set and Clear
• Interrupt Signaling
  • Edge or level
  • Active high or low
• Availability of optional Processor Version Register

For details, see the MicroBlaze Processor Reference Guide.