MicroBlaze Processor Performance
TheMicroBlaze™ architecture balances execution performance against implementation size. It is important to keep in mind that benchmark performance will vary depending on the processor configuration, implementation tool results, targeted FPGA architecture, and device speed grade.
The performance numbers presented below are best case comparison numbers achieved under conditions equivalent to those used by in the industry. The results do not represent typical system performance for general embedded applications. The maximum performance and maximum clock frequency will vary from one design to another according to configuration options used.
MicroBlaze Processor v7.00 Performance Benchmark
The Dhrystone 2.1 industry standard benchmark measures the performance of a processor executing a specific distribution of operations. The performance is reported as the number of Dhrystone instructions executed per second (DMIPS).
The following table represents the maximum Dhrystone performance at which the MicroBlaze v7.00 core can deliver. The targeted system includes a UART and timer necessary for the benchmark. MicroBlaze is configured with a hard multiplier, barrel shifter and one FSL port. Execution is done from on-chip memory.
| MicroBlaze v7.10 Core Configured for DMIPS (EDK 10.1) |
| FPGA |
Size |
Clock Frequency |
Dhrystone 2.1 |
Performance |
| MicroBlaze v7.10 Performance Optimized Configuration for Virtex |
Virtex®-5 (5VLX50)
No MMU
5-stage
|
1,027 LUTs |
235 MHz |
280 DMIPS |
1.19 DMIPS/MHz |
| MicroBlaze v7.10 Performance and Size Optimized Configurations for Spartan |
Spartan®-3 (3SD1800A-5)
5-stage
|
1,809 LUTs |
105 MHz |
125 DMIPS |
1.19 DMIPS/MHz |
Spartan-3 (3SD1800A-5)
3-stage
|
1,324 LUTs |
115 MHz |
110 DMIPS |
0.95 DMIPS/MHz |
|