ISE Simulator
ISE Simulator offers an easy way to perform HDL simulation within the ISE design environment.
ISE™ Simulator provides a complete, full-featured HDL simulator integrated within ISE. Now, HDL simulation can be an even more fundamental step within your design flow with the tight integration of the ISE Simulator within your design environment.
ISE Simulator provides:
- ISE Simulator Lite is included for Free with ISE™ WebPACK™ and ISE Foundation™ software ; limited to 50,000 lines of HDL source code.
- ISE Simulator is available as a low-cost optional add-on to ISE Foundation software; supports any design density
- Mixed VHDL and Verilog simulation
- An integrated wave editor for test bench creation
- Behavioral/RTL simulation prior to synthesis
- Timing simulation after place and route or fitting
- Design hierarchy, waveform, and console views
- Source-level debugging capabilities
- Command-line console features TCL interface
- "Generate Expected Results" process generates expected design output behavior based on input stimulus
- The ability to generate Value Change Dump (VCD) or XAD files for use in power estimation (XPower)
Device Family Support
- Virtex™-5 LX, LXT, SXT, FXT
- Virtex-4 FX, LX, SX
- Virtex-II Pro
- Virtex-II
- Virtex-E
- Virtex
|
- Spartan™-3A DSP
- Spartan-3A, 3AN
- Spartan-3, 3E
- Spartan-II, IIE
- CoolRunner™-II
- CoolRunner XPLA3
- XC9500
|
System Requirements
- Microsoft Windows XP Professional (32-bit only)
- Microsoft Windows Vista Business (32-bit only)
- Red Hat Enterprise Linux 4 WS (32-bit and 64-bit)
- Red Hat Enterprise Linux 5 Desktop (32-bit and 64-bit)
- SUSE Linux Enterprise 10 (32-bit and 64-bit)
Note: SUSE Enterprise 10 Desktop Server products are binary compatible
Software Requirements
Key Features
- Simulation support for all of Xilinx leading devices
- VHDL-93 language support
- Verilog-2001 language support
- An intuitive user interface including:
- Waveform Editor window (used for graphical test bench creation)
- Waveform Display window
- Hierarchy Browser window
- Signals window
- Advanced Search capability to find signals in any scope of design
- Filter capability to view only what is pertinent to your needs
- Tcl-based Simulation Console window
- Signal grouping
- Support for incremental compilation
- Complete printing support
- Source code debugging for accelerating design troubleshooting and timing simulations
|
