AXI Bus Functional Model (BFM)
The ability to purchase AXI BFM has been discontinued as of December 1, 2016. The existing AXI-BFM licenses will work perpetually in releases through 2016.4, but will not be supported after the Vivado 2016.4 release.
AXI BFM will be replaced by Xilinx AXI Verification IP in CY2017. For more information please contact your Local Xilinx Sales Contact.
The AXI Bus Functional Models (BFMs), developed for Xilinx by Cadence Design Systems, support the simulation of customer-designed AXI-based IP. AXI BFMs support all versions of AXI (AXI3, AXI4, AXI4-Lite and AXI4-Stream). The BFMs are delivered as encrypted Verilog modules. BFM operation is controlled via a sequence of Verilog tasks contained in a Verilog-syntax text file. The API for the Verilog tasks is described in the AXI BFM User Guide.
The AXI BFM can be used to verify connectivity and basic functionality of AXI masters and AXI slaves with the custom RTL design flow. The AXI BFM provides example test benches and tests that demonstrate the abilities of AXI3, AXI4, AXI4-Lite and AXI4-Stream Master/Slave BFM pair. These examples can be used as a starting point to create tests for custom RTL design with AXI3, AXI4, AXI4-Lite and AXI4-Stream interface. The examples can be accessed from CORE Generator or standalone web download.
The AXI BFM can also be used for embedded designs using Xilinx Platform Studio (XPS). The AXI BFM is available as part of the CIP wizard to create an AXI-based IP with AXI BFM solution. The AXI BFM is also provided as separate pcores that can be accessed from the XPS IP catalog.
There are no evaluation licenses for AXI BFM IP.
Key Features & Benefits
- Supports all protocol data widths and address widths, transfer types and responses
- Transaction level protocol checking (burst type, length, size, lock type, cache type)
- Behavioral Verilog Syntax
- Verilog Task-based API
- Delivered in ISE, enabled by a Xilinx-generated license
- Verilog and VHDL example designs and test benches delivered standalone or through CORE Generator for RTL design
- Integrated with XPS as a pcore or as an option with CIP wizard
- Supported Simulators: Aldec Riviera-PRO, Cadence Incisive Enterprise Simulator, ISE Simulator, Mentor Graphics ModelSim and Synopsys VCS
- Status: Discontinued
- Part Number: DO-AXI-BFM
- License: Xilinx End User License Agreement
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