Product Details
Documentation
Device Family Support
- Spartan-3E
- Spartan-3
- Virtex-4 FX
- Virtex-4 LX
- Virtex-4 SX
- Virtex-5 LX
- Virtex-II
- Virtex-II Pro
- Spartan-3A DSP
Requirements
- ISE™ 9.1i IP Update 2 or later
The IEEE 802.16e CTC Encoder Core performs duo binary Turbo Encoding of channel data as described in Section 8.4.9 of the IEEE Std 802,16e specification. The coding scheme is a parallel concatenated convolutional code with an input data block of 2N bits. Through parallel processing of the two convolutional encoders, the LogiCORE™ IP is capable of achieving a high throughput encode data rate in excess of 450Mb/s in the slowest speed grade of Virtex™-4 FPGA.
Key Features
- Performs Convolutional Turbo encoding compliant with the IEEE 802.16e-2005 mobile WiMAX standard.
- Support for all ‘mandatory’ modulation schemes plus ‘optional’ 64-QAM mode.
- Supports Hybrid ARQ for all block sizes.
- Simultaneous C1 and C2 encoding plus triple buffered memory delivers high throughput encoding rates. Blk size 480 = 580Mb/s*, Blk size 24 = 461Mb/s* {* = V4 (-10)}
- Optional Control Signals enable
- Core Generator Module enables easy parameterization
- Now supports the following rev of 802.16 spec: IEEE802.16e-2004/Cor1/D5
- Compliant with IEEE 802.16e-2004 Cor1/D5
