Product Details
Documentation
Device Family Support
- Spartan-3
- Spartan-3A DSP
- Spartan-3E
- Virtex-4 FX
- Virtex-4 LX
- Virtex-4 SX
- Virtex-5 LX
- Virtex-5 LXT
- Virtex-5 SXT
- Virtex-II
- Virtex-II Pro
Requirements
The DVB-S.2 FEC Encoder core provides a complete Forward Error Correction (FEC) encoding solution for DVB-S.2. This core consists of Outer (BCH), Inner (LDPC) encoding and bit-interleaving stages. The bit interleaver supports the interleaving required by all modulation types, which may be QPSK, 8PSK, 16APSK or 32APSK. All parameters can be changed on a frame-by-frame basis.
Key Features
- Complete Forward Error Correction solution for DVB-S2 (satellite) (ETSI EN 302 307 v1.1.1,2005-03) - BCH Encoder, LDPC (low density parity check) Encoder, Interleaver
- Normal (64k), short frames (16k) and all code rates supported
- Frame length, rates and modulation type can be changed dynamically supporting Adpative Coding Modulation (ACM)
- Serial and parallel (up to 8 bits) input options giving area versus speed tradeoff
- Foutput options (up to 5 bits) facilitating easier matching with Tx symbol mapper
- Typical max clock for Virtex-5-3 is 243 MHz (4-bit parallel input)
- Throughput of over 900 Mbit/s for normal frame, rate 1/2
- Buffering on input and output, with option for reduced encoding latency
- Full range of handshake signals for easy insertion into baseline DVB-S2.
