Product Details
Documentation
Device Family Support
- Spartan-3
- Virtex-4 LX
- Virtex-4 SX
- Virtex-5 LX
Requirements
The Xilinx H.264 Context Adaptive Binary Arithmetic Coder (CABAC) core is a fully functional design block for implementation on Xilinx FPGAs.
For each slice to encode, the CABAC core generates a compressed bitstream. The format of the bitstream conforms to specifications defined by the ITU-T Video Coding Experts Group (VCEG) together with the ISO/IEC Moving Picture Experts Group (MPEG). These specifications are the product of a collective partnership effort known as the Joint Video Team (JVT).
Key Features
- Designed to H.264/MPEG-4 Part 10 Main/High/High Ext. standard
- Support for up to HD 1080i and 1080p/60 fps
- Output stream compliant with International Standard ISO/IEC 14496-10:2005 (E) Rec. H.264 (E)
- YUV 4:2:0 format support
- Fixed Context Model Initialization
- Interlaced streams
