Product Details
Documentation
Device Family Support
- Spartan-3A DSP
- Virtex-4 LX
- Virtex-4 SX
- Virtex-5 LX
Requirements
The Xilinx® H.264 Motion Estimation Engine Core Version 1.0 core is a fully functional design block for Xilinx FPGAs. The Motion Estimation core accepts input parameters and macroblocks and generates output motion vectors and Sum of Absolute (SAD) values in accordance with the ITU-T Video Coding Experts Group (VCEG) together with the ISO/IEC Moving Picture Experts Group (MPEG) as the product of a collective partnership effort known as the Joint Video Team (JVT).
Key Features
- Supports H.264/MPEG-4 Part10 Baseline/Main/High Profiles @ Level 4.2
- Designed to International Standard ISO/IEC 14496-10:2005 (E) Rec. H.264 (E)
- 1080i@60 fields per second operation at 225 MHz
- 720p@30 frames per second operation at 150 MHz
- Integrated variable block pattern generation
- 8x4 blocks search for full pel locations
- 112 x 128 search range
