SPI-4 Phase 2 Interface Solutions (DO-DI-POSL4MC)

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SPI-4 Phase 2 Interface Solutions

Device Family Support

Virtex-4 FX
Virtex-4 LX
Virtex-4 SX
Virtex-5 FXT
Virtex-5 LX
Virtex-5 LXT
Virtex-5 SXT
Virtex-II
Virtex-II Pro

Requirements

ISE 10.1

The Xilinx SPI-4 Phase 2 core provides a fully compliant Packet-Over-SONET/SDH (POS) solution, which can be quickly integrated into networking systems.

Through user-configurable options, the Xilinx SPI-4.2 core provides ultimate flexibility while seamlessly interoperating with industry leading ASSPs to maximize the data transfer bandwidth. The Xilinx SPI-4.2 core is fully compliant with the OIF's System Packet Interface Level 4 (SPI-4) Phase 2 standard, as well as the SATURN® Development Group's POS-PHY Level 4 (PL4) interface specification.

Key Features

Up to 600 MHz DDR on SPI-4.2 interface supporting 1.2 Gbps pin pair total bandwidth
Supports Static and Dynamic Phase Alignment utilizing ChipSync™ technology
Bandwidth optimized source core achieves optimal bus throughput without additional FPGA resources
Flexible clocking options utilizing DCM, PMCD, global, and regional clocking resources
SelectIO™ technology supports flexible pin assignment
Configurable 64-bit or 128-bit user interface, both supporting full bandwidth capabilities
Supports unsegmented burst sizes up to 16K
Optional continuous DPA window monitoring
Optional advanced DPA diagnostics
Multiple core support: more than 4 cores can be implemented in a single device
Sink and Source cores independently configured through Xilinx CORE Generator™ system for easy customization
Supports all Virtex™-5 and Virtex-4 device and package configurations
Supports 1 to 256 addressable channels with fully configurable SPI-4.2 calendar interface

The SPI-4.2 core interfaces between Physical (PHY) and Link layer devices within networking applications, and supports static or dynamic alignment configurations. The core communicates between devices, using the SPI-4.2 interface standard at up to 1.2 Gps/pin, enabling OC-192 POS, ATM, and 10 Gb/ps Ethernet applications.

The Xilinx POS-PHY strategy is to develop complementary cores that interoperate with leading ASSP developers. The Xilinx SPI-4.2 core has been verified in hardware to interoperate with PHY devices from PMC-Sierra (S/UNI® -9953 (PM5390)), Vitesse (Meigs-II™ (VSC7321)), and Intel® (IXF1810x family, IXP2800 Network Processor).

Related Information

Related Products

1.	How is flow control implemented?
2.	How does the calendar work and what is the relationship to the data path?
3.	How does the core store data for different channels?
4.	What is the purpose of DIP-4 and DIP4Err? And, how is the data sent on the SPI-4.2 Interface validated?
5.	What are the handshakes between the PHY and Link devices after reset?
6.	Where do I get information known issues?
7.	Who do I contact if I have SPI-4.2 technical questions?
8.	How do I get an evaluation copy?
9.	What is the power consumption of the SPI-4.2 core?
10.	What software supports the SPI-4.2 core?

1. How is flow control implemented?
The Flow Control information is sent on the SPI-4.2 interface signals TSTAT[1:0] and RSTAT[1:0] There are 2-bits of information for each channel 00=Starving, 01=Hungry, 10=Satisfied, 11=Framing Pattern Status is transmitted serially on the SPI-4.2 Interface The SPI-4.2 core transmits/receives the status information on the User Interface for each channel individually (two bits per channel) The SPI-4.2 core passes Flow Control data through the core PASSIVE Implementation The order for transmitting status is determined by thecalendar program Required to be the same for the PHY and Link device [back to top]
2. How does the calendar work and what is the relationship to the data path?
The calendar is programmed by dedicated signals on the User Interface. It controls the order that the flow control status is sent and received on the SPI-4.2 Interface. The calendar does not directly effect the data path on the SPI-4.2 I/F. The Source core can present the status information in two ways: an Addressable Status Interface or a Transparent Status Interface.The Addressable Status Interface allows the user to access (poll) the status of 16-channels at one time. The Transparent Status Interface presents the status information as it is received on TStat[1:0] with minimal latency. [back to top]
3. How does the core store data for different channels?
The Source and Sink logic have only one FIFO each The User Sink FIFO I/F presents data in the same order it is received across the SPI-4.2 bus The Source logic transmits data (TDAT) in the same sequence it is loaded into source FIFO Flow control information does not affect Source data order The user must perform per channel flow control at the Source FIFO write side The user can force idles onto the SPI-4.2 TDAT, and this halts all channels (blocking) The Channel address (port) is agnostic to the channel configuration The full 8-bit channel address is supported regardless of the core configuration [back to top]
4. What is the purpose of DIP-4 and DIP4Err? And, how is the data sent on the SPI-4.2 Interface validated?
The purpose is to verify ingress cell data Uses DIP-4 (4-bit Diagonal Interleaved Parity). Embedded in all control words by the egress device. FLOW Egress core calculates DIP-4 across all data words proceeding the control word. Ingress core calculates the identical DIP-4 (to verify cell integrity.) If a mismatch is detected, a DIP-4 error (DIP4Err) is driven on the User Interface [back to top]
5. What are the handshakes between the PHY and Link devices after reset?
After Reset: Training patterns sent on data bus A framing sequence ("11") is sent on status bus The transmission of training patterns is repeated until: Valid information (non-framing status) is received on the status bus Valid data can then be transmitted on the data bus [back to top]
6. Where do I get information on known issues?
Search for POS PHY or SPI-4.2 in the answer record database at support.xilinx.com Readme files are provided with the design files [back to top]
7. How do I get an evaluation copy?
Xilinx provides two ways to evaluate the SPI-4.2 core: Simulation Only, and Full System Hardware Evaluation. Simulation Only Evaluation (enabled by default) allows you to simulate the SPI-4.2 core and evaluate the behavior of the ports, utilizing the provided RTL test bench and loopback modules. Full System Hardware Evaluation for the SPI-4.2 core allows you to do everything you can do with the fully licensed IP core, including configure, place and route, simulate, estimate timing, and program a Xilinx FPGA device. Contact your local FAE to request this evaluation core. Visit the SPI-4.2 Evaluation Page for more details. [back to top]
8. What is the power consumption of the SPI-4.2 core?
For Virtex-5, Virtex-4, Virtex-II Pro, Virtex-II and SPI-4.2 Lite see IP Release Notes Guide [back to top]
9. What software supports the SPI-4.2 core?
The SPI-4.2 Core for Virtex-4/5 is supported with ISE 10.1 and the Xilinx CORE Generator™ software 10.1 or later. The SPI-4.2 Lite core is supported with ISE 10.1.2 or later and the Xilinx CORE Generator software 9.1i with IP Update #1. [back to top]

SPI-4 Phase 2 Interface Solutions (DO-DI-POSL4MC)

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