Product Details
Documentation
Device Family Support
- Spartan-3E
- Spartan-3
- Spartan-II
- Virtex-4 FX
- Virtex-4 LX
- Spartan-3A
- Virtex-4 SX
- Virtex-5 LX
- Virtex-5 LXT
- Spartan-3AN
- Virtex-II
- Spartan-3A DSP
- Virtex-II Pro
Requirements
- ISE™ 6.1i Update #1 and later - core v1.0
- ISE 9.1i Update #2 and later - core v2.1
This Turbo Convolutional Code (TCC) Decoder implements the CDMA2000/3GPP2 mobile communication system specification. This LogiCORE module is designed to work with the CDMA2000/3GPP2 TCC Encoder LogiCORE module to provide an extremely effective way of transmitting data reliably over noisy data channels. The decoder implements the MAX or MAX* algorithm. It allows the user to dynamically select the number of iterations, from 1 to 16. The core expects two's complement fractional numbers as inputs and also uses this format for the internal calculations. It supports a sliding window size of 32 or 64. The decoder works with all CDMA2000/3GPP2 code rates. It is designed to use internal or external RAM for data storage.
Key Features
- Implements full 3GPP2 interleaver
- Supports full 3GPP2 block size range - 378-20730 (core v1.0), 122-12282 (core v2.1)
- User selectable use of MAX, MAX* or MAXSCALE algorithms – allows user to trade off performance against memory resources
- Input bit widths parametrizable (from 2-5 integer + 1-4 fractional bits with core v2.1)
- Dynamically selectable number iterations from 1-15
- Sliding window sizes of 32 or 64 – reduces memory resources
- Internal or external RAM data storage
| TCC Decoder Core Version | 3GPP2 Specification Supported |
|---|
| V1.0 | 'Rev. C' (C.S0002-C_v1.0) |
| V2.1 | ‘EVDO rev. A/B’ (C.S0024-a_v2.0, C.S0024-b_v1.0) |
