Product Details
Documentation
Device Family Support
- Spartan-3
- Spartan-3 XA
- Spartan-3A
- Spartan-3A DSP
- Spartan-3E
- Spartan-3E XA
- Virtex-4 FX
- Virtex-4 FX XA
- Virtex-4 LX
- Virtex-4 SX
- Virtex-5 LX
- Virtex-5 LXT
- Virtex-5 SXT
- Virtex-II
- Virtex-II Pro
Requirements
The Finite Impulse Response (FIR) Filter is the one of the most ubiquitous and fundamental building blocks in DSP systems. Although its algorithm is extremely simple, the variants on the implementation specifics can be immense and a large time sink for hardware engineers today, especially in filter dominated systems like Digital Radios.
The FIR Compiler v4.0 reduces filter implementation time to the push of a button, while also providing users with the ability to make trade-offs between differing hardware architectures of their FIR Filter specification.
The FIR Compiler supports three different filter architectures:
- Pipelined Direct-Form based Multiply Accumulate (MAC) FIR
- Transposed Direct-Form based MACFIR
- Distributed Arithmetic (DAFIR) FIR
Furthermore, Virtex™-5 and Spartan™-3A DSP performance reaches the maximum 450 MHz (-1) and 250 MHz (-3) achievable and greatly reduces the number of resources required versus lower performance FPGA devices.
New Features in v4.0 :
- Poly-phase filter bank structure for Channelizer applications
- Extended Data and Coefficient Width range up to 49 bits
- Transposed Direct-Form MAC architecture.
- Capability to share control and coefficient memory resources up to 16 parallel data paths
- Virtex®-5 and Spartan®-3A DSP support added for Distributed Arithmetic architecture.
- Behavioral VHDL model for fast HDL simulations.
Key Features
- 450 MHz maximum performance solutions for Virtex-5 devices (-1speed grades)
- 250 MHz maximum performance solutions for Spartan-3A DSPdevices (-4 speed grade)
- Support for typical algorithmic requirements: single-rate, fractional rate, multi-rate, Hilbert, and zero-packed interpolated
- Multiple implementation architectures: DAFIR, Adder Tree based MACFIR (suitable for Spartan devices) and Adder Chain based MACFIR (suitable for DSP48 enabled devices)
- Supports 2-1024 taps
- Automatic control of hardware folding for the most compact implementation
- Supports up to 32 channels and 32 interpolation and decimation factor
- Support for Reloadable Coefficients and up to 16 coefficient sets
- Floating Point Coefficient entry support and quantization diagnoses
- Automatic Coefficent structure optimizations to reduce area consumed: Symmetry and Halfband
- Support for Multiple DSP48 Column Filter implementations
- Automatic selection of Block vs Distributed Memory for Data and Coefficient storage
- Instantaneous Resource Estimation of DSP48/MULT18x18 and BRAM
