Memory Interfaces Advantage

Highest Bandwidth Memory Interfaces Made Easy
Reliable source-synchronous data capture is the most critical, and most difficult, challenge for building high-performance memory interfaces. Virtex™-4 FPGAs help you achieve your memory interfaces performance targets in the shortest possible time by:

• Ensuring reliable read data capture through ChipSync™ technology.
• Controlling system noise with innovative package design.
• Delivering complete solutions with easy to use software.

Table 1: Maximum Bandwidth for Memory Interfaces
Interfaces	Virtex-4 FPGAs	Altera Stratix II FPGAs	Virtex-4 Advantage
DDR2 SDRAM	231 Gbps	77 Gbps	3x
QDRII SRAM	259 Gbps	72 Gbps	3.6x
DDR SDRAM	173 Gbps	58 Gbps	3x
RLDRAM II	259 Gbps	86 Gbps	3x
Note: Based on competitor’s published data sheet numbers. Bandwidth = Data Rate x Data Width.

Reliable Read Data Capture

Xilinx enhanced the performance of the world's fastest FPGAs by incorporating Chipsync technology into every Virtex-4 I/O. A fine-resolution, multi-tap delay block ensures centering of the clock to the middle of the data valid window. Run-time calibration maximizes the design margins by adjusting for process, voltage and temperature variations. This unique Xilinx method is not available in any other FPGA, ASIC, or ASSP device.

Figure 1

Calibration with ChipSync variable delay technology is the only solution that ensures accurate centering of the clock to the data valid window under changing system conditions (process, voltage and temperature).

Competing devices use a fixed phase-shift delay for capturing read data. This approach was adequate for lower data rates. However, the delay value must be fixed at design time and the circuits provide no adjustment for variations in process, voltage and temperature. Furthermore, each clock (strobe) in a multi-clock (strobe) system relies on this single value, with no delay adjustment for skew due to different routing paths. As a result, design margins shrink. This increases the risk of bit errors, because the centering of the clock (strobe) to the data-valid window may no longer be valid for all clock (strobe) signals.

Innovative Package Design Ensures Superior Signal Integrity

Wide busses enable higher bandwidth, but they create large simultaneous switching output (SSO) noise problems that can affect the performance and reliability of your interfaces. Xilinx SparseChevron package technology provides an innovative distribution of power and ground pins that controls noise. Signal integrity expert Dr. Howard Johnson has demonstrated that Virtex-4 FPGAs in SparseChevron packaging produce 7x less noise than competing devices.

Figure 2

The unique SparseChevron pin pattern used in Virtex-4 packaging places a power and ground pin pair next to every signal pin. This design helps control signal integrity problems at the chip level. Competing devices, in contrast, use pin patterns that leave many regions of the package devoid of returns.

Flexible I/O placement simplifies board design

Virtex-4 FPGAs simplify PCB layout by eliminating bank restrictions on I/O pin assignment for memory interfaces.  Compared to competing FPGAs, which restrict memory interface I/O pin assignment to only half of the available I/O banks , Virtex-4 FPGAs can help shrink design time and reduce manufacturing costs by reducing PCB layer count.

Complete solutions with easy-to-use software

Xilinx provides complete memory interface solutions for all popular memory interfaces (DDR2 SDRAM, DDR SDRAM, QDR II SRAM, RLDRAM II) that are hardware verified using our Advanced Memory Development System ML461. The Memory Interface Generator tool, available as a free download from Xilinx, helps you create customized interfaces, including HDL code and pin placement, quickly and easily.

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