Low Power Consumption

1 to 5 Watts Lower Power Per FPGA
Meeting your power budget is essential for attaining system performance and cost goals. Low power enables higher clock frequency, higher reliability, better noise margins, and reduced capital and operational costs. Measurements and analysis using Xilinx tools and revised tools from competing vendor show Virtex™-4 consuming up to 73% lower static power and up to 86% lower dynamic power than competing 90nm FPGAs.

Meet performance goals without breaking your power budget

Figure 1

LX60 vs. 2S60. Target Frequency = 200 MHz. Worst-case process. 20K LUTs, 20K Flip-Flops. 1 Mbit On-Chip RAM, 64 DSP Blocks, 128 2.5V I/Os Based on Xilinx tool v4.1 and competitor tool v2.1

Total power comparison data

Figure 2

Measurements show 1-5W lower power per FPGA

Design Details

• Static power at Tj = 85°C*
• Dynamic power at 200 MHz for equivalent logic and memory
• 50% of LUTs and FFs in Virtex-4 and equivalent ALUTS and FFs in competing FPGA, 12.5 % toggle rate
• All M4K blocks used in competing FPGA and equivalent 18 Kb Block RAM in Virtex-4 FPGA

*The importance of temperature : In a typical environment the junction temperature can easily reach 85°C and static power becomes a significant part of total power, especially for vendors who haven't optimized leakage. To provide users with realistic estimates, Xilinx uses junction temperature at 85°C. Vendors using only ambient temperature/25°C are providing misleading data. Junction temperature, Tj is almost always higher than 25°C for real world designs.