Signal Integrity

7x Less SSO Noise
Lab measurements and simulations conducted by renowned signal integrity expert Dr. Howard Johnson show that the advanced packaging technology of Virtex™-4 FPGAs provides up to seven times less crosstalk compared to competing 90nm FPGAs.

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Signal Integrity Seminars with Dr. Howard Johnson:
New!: Power Integrity: PDS Design for FPGA Systems
Jitter Effects in Modern System Design II
Jitter Effects in Modern System Design
BGA Crosstalk in Depth
BGA Crosstalk
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Figure 1

"Accumulating" Test Comparison of Virtex-4 FPGAs vs. Stratix-II

When building wide single-ended I/O interfaces such as DDR2, DDR, RLDRAM-II, and QDR II memory interfaces, controlling crosstalk becomes a significant challenge for achieving breakthrough system performance. As a result, users designing any type of memory interfaces must consider the signal integrity (SI) characteristics of their FPGA solutions.

Lab measurements and simulations conducted by renowned signal integrity expert Dr. Howard Johnson show that the advanced packaging technology of Virtex-4 FPGAs provides up to seven times less crosstalk compared to competing 90nm FPGAs.

Advanced Packaging Controls Crosstalk/SSO Noise

Virtex-4 FPGAs incorporate advanced packaging technology to deliver significant system design benefits that shrink design cycles and reduce design costs:

  • New SparseChevron pin out pattern
  • Best on-package decoupling capacitor solution
  • Continuous Power/GND planes
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