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SelectIO
Virtex™-4 FPGAs make it easy to build robust high-speed memory and networking interfaces. All Virtex-4 platforms include configurable, high-performance SelectIO™ technology to support a wide variety of I/O standards. Virtex-4 FPGAs provide up to 960 user I/Os supporting over 20 single-ended and differential electrical I/O standards to enable several parallel system interface standards on one device. New ChipSync™ technology built into every I/O block makes source-synchronous interfacing to the latest high-speed components easy. Plus, powered with XCITE technology, each I/O block deliver on-chip active I/O termination eliminating external termination resistors to increase signal integrity, and save board space, and reduce system cost.
ChipSync Source-synchronous Interface Technology in Every I/O!
To ensure reliable data transfer between a new generation of high-speed devices, hardware designers are turning to source-synchronous design techniques, in which the component sending the data generates and issues its own clock signal along with the data that it transmits. ChipSync technology simplifies component interface design with critical built-in circuitry that is available in every Virtex-4 I/O.
ChipSync Technology Automatically Manages Lower Internal FPGA Frequencies
- ChipSync technology simplifies design and boosts performance with an embedded SERDES to serialize and de-serialize parallel bus interfaces to match the data rate to the speed of the internal FPGA circuits. ChipSync technology enables data rates greater than 1 Gbps for differential I/O and over 600 Mbps for single-ended I/O. This ability simplifies the design of interfaces such
as SPI-4.2, XSBI, SFI-4 as well as RapidIO and HyperTransport.
ChipSync Technology Eliminates Setup and Hold Time Issues
- ChipSync technology simplifies the implementation of network interfaces and memory interfaces for high-speed memories, including DDR 2 SDRAM, QDR II SRAM, FCRAM II, and RLDRAM II, by compensating routing issues that produce skew between data and clock signals. Built-in circuitry enables the delay of each data and clock channel, in 80 ps increments, to meet the setup and hold
requirements for reliable data capture. To address extreme levels of skew greater than a bit interval, ChipSync technology provides a Bitslip capability. An optional training pattern simplifies the task of aligning data words across all channels.
Clock-Aware I/Os
- With clock-aware I/Os, ChipSync technology enables simultaneous implementation of multiple source-synchronous interfaces. Xesium clocking makes this possible with up to 24 clock regions per device. Each region can have up to 6 I/Os acting as clock sources for data capture. Up to 95 I/Os can be clocked by a single I/O clock, providing both great clock flexibility as well as a large number of clocks.
SelectIO Input/Output Block (IOB)
Each IOB is user-configurable to serve as input, output, or bi-directional I/O. All I/Os support single-ended and differential electrical standards.
- Single-ended electrical standard support for
LVTTL, LVCMOS (3.3V, 2.5V, 1.8V, and 1.5V), PCI (33 and
66 MHz), PCI-X, GTL and GTL+, HSTL 1.5V and 1.8V (Class
I, II, III, and IV), and SSTL 2.5V and 1.8V (Class I and
II).
- Differential electrical standard support for 840
LVDS, Extended LVDS (2.5V), Bus LVDS, ULVDS, LVPECL 2.5V,
and HyperTransport (LDT). All I/Os can be configured as
differential I/O without any placement restriction for
flexibility.
- Built-in double-data rate input and output registers
enable implementation of DDR and QDR interfaces.
- Seventeen I/O banks support electrical standards
spanning across multiple voltages with independent reference
voltages.
XCITE Digitally Controlled Impedance Technology- A Xilinx Innovation
I/O termination is required to maintain signal integrity. With hundreds of I/Os and advanced package technologies, external termination resistors are no longer viable. All Virtex-4 I/O structures include third-generation Xilinx Controlled Impedance Technology (XCITE) on-chip active I/O termination. These built-in circuits dynamically eliminate drive strength variation resulting from process, temperature, and voltage fluctuations.
Virtex-4 XCITE DCI Technology Highlights
- Series, parallel and differential termination for single-ended and differential standards.
- Maximum flexibility with support of series and
parallel termination on all I/O banks.
- Input, output, bidirectional
and differential I/O
support.
- Wide series impedance range: 20 ohm - 100 ohm
- Popular standard support including LVDS, LVDSEXT,
LDT, ULVDS, LVCMOS, LVTTL, SSTL, HSTL, GTL, and GTLP
- Full- and half-impedance input buffers
| XCITE DCI Technology Advantages |
| Advantage |
Details |
| 2nd generation technology |
Proven in the field and used extensively
by customers |
| Lowers cost |
Fewer resistors, fewer PCB traces
and smaller board area, result in lower PCB costs. |
| Absolute I/O Flexibility |
Any termination on any I/O bank.
Non-XCITE technology alternatives deliver limited functionality. |
| Maximum I/O Bandwidth |
Less ringing and reflections maximize
I/O bandwidth. |
| Immunity to temperature and
voltage changes |
Temperature and voltage variations
lead to significant impedance mismatches. XCITE technology
dynamically adjusts on-chip impedance to such variations
reducing and improving reliability. |
| Eliminates stub reflection |
Improves discrete termination techniques
by eliminating the distance between the package pin
and resistor. |
| Increases system reliability |
Fewer components on board, deliver
higher reliability |
| SelectIO Technology Provides Integrated
Support for These Standards |
| Parallel Standard (Single ended/Differential) |
Interface |
Max Data Rate per channel |
| PCI |
32-bit/33 MHz, 64- bit/66 MHz, 3.3V PCI |
33/66 Mbps |
| PCI-X |
64- bit, 133 MHz, 3.3V PCI-X |
133 Mbps |
| 1
Gb Ethernet with GMII |
8- bit GMII |
125 Mbps |
| 10
Gb Ethernet with XGMII |
32-bit HSTL |
312.5 Mbps |
| RapidIO |
8/16- bit LVDS |
500 Mbps |
| POS
PHY Level 3 |
32-bit CMOS |
104 Mbps |
| POS
PHY Level 4 |
16-bit LVDS |
840 Mbps |
| Flexbus
4 |
64-bit HSTL |
200 Mbps |
| HyperTransport |
2/4/8/16/32 bit HyperTransport (LDT) |
800 Mbps |
| CSIX |
32-bit HSTL |
200 Mbps |
| XSBI |
16-bit LVDS |
644 Mbps |
| SFI-4 |
16-bit LVDS |
622
Mbps |
| SelectIO supports single-ended and differential standards. |
Protocol Implementation and Bridging
- Soft IP cores implement parallel interface standard protocols and enable you to bridge across them.
Interoperability
- Xilinx works with industry leading ASSP vendors and participates in interoperability testing events to deliver proven standard interoperability.
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