XtremeDSP Slice

    

Virtex™-4 FPGAs provide blazing DSP performance with unrivalled economy. The XtremeDSP™ slices available in all Virtex-4 family members facilitate new DSP algorithms and higher levels of DSP integration than previously available in FPGAs, while delivering low power consumption, very high performance, and efficient silicon utilization. With up to 512 XtremeDSP slices operating at 500 MHz, you can solve complex challenges, such as implementing:

• Hundreds of IF-to-baseband down-conversion channels.
• 128X chip-rate processing for 3G spread spectrum systems.
• High definition H.264 and MPEG-4 encode/decode algorithms.

XtremeDSP Slices deliver high-performance, low power, versatility, and efficiency

The XtremeDSP slice forms the basis of a versatile, coarse grain DSP architecture, enabling you to efficiently add powerful FPGA-based DSP functionality to your system.

• XtremeDSP Slices have been custom designed in silicon to achieve 500 MHz performance independently or when combined together within a column to implement DSP functions.
• Each XtremeDSP Slice draws only 2.3 mW/100 MHz, at a typical toggle rate of 38%, just 6% of the power consumption of previous FPGA DSP implementations.
• The XtremeDSP Slice supports over 40 dynamically controlled operating modes including; multiplier, multiplier-accumulator, multiplier-adder/subtractor, three input adder, barrel shifter, wide bus multiplexers, or wide counters.
• Cascade XtremeDSP Slices without using FPGA fabric or routing resources to perform wide math functions, DSP filters, and complex arithmetic.

Architectural highlights of the XtremeDSP slices:

• 18-bit by 18-bit, two's complement multiplier with full precision 36-bit result, sign extended to 48 bits.
• Three input, flexible 48-bit adder/subtracter with optional registered accumulation feedback.
• Over 40 dynamic user-controller operating modes to adapt XtremeDSP slice functions from clock cycle to clock cycle.
• Cascading, 18-bit B bus, supporting input sample propagation.
• Cascading, 48-bit P bus, supporting output propagation of partial results.
• Multi-precision multiplier and arithmetic support with 17-bit operand right shift to align wide multiplier partial products (parallel or sequential multiplication).
• Symmetric intelligent rounding support for greater computational accuracy.
• Performance-enhancing pipeline options for control and data signals are selectable by configuration bits.
• Input port "C" typically used for multiply, add, large three-operand addition or flexible rounding mode.
• Separate reset and clock enable for control and data registers.