Low Cost Advantage

Reduce Cost through System Integration
Virtex™-5 FPGAs reduce the cost of developing and manufacturing electronic systems by enabling engineers to meet design targets quickly and easily, minimize power consumption, ensure signal integrity, and simplify PCB design. See the Hard IP Area Saving Case Study.

65nm ExpressFabric Technology

Xilinx 65nm triple-oxide process technology shrinks die size, increases performance, and reduces power consumption. ExpressFabric™ technology with Real 6-input LUT architecture and diagonally symmetric interconnect increases logic utilization and performance by reducing logic levels between registers and creating shorter, faster routing.

Hard IP

Abundant hard IP provides area and power-efficient implementation of key functions with guaranteed performance that simplifies the design and enables you to choose a smaller device.

• Enhanced clock management tiles provide precise, low-jitter clock generation.
• Embedded Block RAM and distributed RAM/FIFO provide flexible memories for data buffering.
• ChipSync™ technology adaptive clock to data centering to ensure reliable memory interfaces.
• SelectIO™ circuitry provides flexible support for a variety of interface standards with on-chip active I/O termination.
• DSP48E slices provide embedded multipliers with optional adders and accumulators.
• PowerPC® 440 processing block (FXT only) offers a built-in industry standard technology for integrating embedded processing systems
• RocketIO™ GTP transceivers provide built-in high-speed serial I/O capability with the industry’s lowest power consumption.
  (RocketIO GTX transceivers for FXT only)
• PCI Express® endpoint blocks designed to work with RocketIO GTP transceivers to provide built-in PCIe connectivity for x1, x4, and x8 interfaces
• 10/100/1000 Ethernet MAC blocks designed to work with RocketIO GTP and GTX transceivers to provide built-in Ethernet connectivity

Hard IP Area Saving Case Study

As shown in Figure 1, the abundant hard IP in Virtex-5 FPGAs provides logic area efficiency that enables you to implement your design in a smaller, less expensive device.

Figure 1

Power consumption and area required to implement a typical design including 8-lane PCIe endpoint.

Table 1: Hard IP Area Saving Case Study : x8 PCI Express
	Xilinx Virtex-5 FPGA (LX30T)	90nm FPGA (XC2SGX60E, F1152)
User design	25,000 LUTs	25,000 LUTs
PCIe	100 LUTs (wrapper to interface to integrated PCIe endpoint block)	9,600 LUTs (core in fabric)
Total logic consumption	25,100 LUTs	34,600 LUTs

Packaging

Sparse chevron packaging simplifies PCB design and reduces manufacturing cost. The unique pinout reduces crosstalk to help eliminate costly board debug and redesign. On-substrate bypass capacitors eliminate hundreds of external capacitors to simplify PCB layout and routing and reduce PCB size. An enhanced pinout for independent I/O banks reduces PCB layer count for additional cost savings.

Solutions

Xilinx pre-engineered, pre-verified IP, development boards, and kits also increase productivity and reduce design time.

Conversion-free Cost-reduction Path for Volume Production
EasyPath™ FPGAs are the industry’s only 65nm customer-specific volume production solution that offers 30-75% cost reduction over standard FPGAs. Compared to structured ASICs, Virtex-5 EasyPath FPGAs offer the industry’s lowest NREs, a migration-free path to volume, 8-12 week lead-times, and support for two bitstreams per device.
More about EasyPath FPGAs

• Contact a Xilinx Sales representative for more details