Low Power Consumption

Beat Your Power Budget

Low power enables higher clock frequency, higher reliability, better noise margins, and reduced capital and operational costs. Virtex™-5 FPGAs offer significant power savings with a combination of 65nm triple-oxide process and real 6-input LUT ExpressFabric™ technology.

You can reduce active power consumption by 35% while keeping leakage current on-par with equivalent logic implementations in 90nm Virtex-4 FPGAs. RocketIO™ GTP transceivers reduce power by 77%, consuming less than 100 mW at 3.2 Gbps. Please see our Power Savings Case Study.

65nm Triple-oxide Technology Reduces Power

Figure 1

Virtex-5 triple-oxide technology for reduced static power.

Virtex-5 FPGAs are built with triple-oxide technology to deliver the optimal balance of performance and power.

• Thin gate oxides deliver highest speed in performance-critical circuits
• Medium-thickness oxides control leackage current in non-performance critical circuits used for configuration and control
• Thick oxides enable higher voltages in I/O circuits

Figure 2

Virtex-5 triple-oxide technology for reduced static power.

Under worst-case operating conditions (85°C), 65nm Virtex-5 FPGAs keep static power on par with 90nm Virtex-4 FPGAs and deliver 35% lower dynamic power while offering 30% higher performance.

Power Savings Case Study

Figure 3

Power consumption and area required to implement a typical design including 8-lane PCIe endpoint.

This design example shows how 65nm triple-oxide technology and built-in hard IP, such as PCIe® endpoint blocks, provide lower power than competing FPGAs.

Table 1: Power Savings Case Study : x8 PCI Express
	Xilinx Virtex-5 FPGA (LX30T)	90nm FPGA (2SGX60E, F1152)
Transceiver	745 mW ( RocketIO GTP)	1010 mW
PCIe	885 mW (block + wrapper)	836 mW (core in fabric)
Static power	424 mW	1591 mW
Total power consumption	2054 mW	3437 mW