System Monitor

Monitor on-chip and off-chip parameters with built-in ADC

The Virtex™-5 FPGA System Monitor provides an integrated solution for thermal management and the measurement of on-chip power supply voltages. Full access to the System Monitor via a JTAG interface enables a powerful tool for debug and testing during hardware development and manufacturing. On-chip access to System Monitor enables incorporation into the overall system management infrastructure for improved performance and reliability. User defined alarms warn of critical temperature or power supply conditions.

System Monitor is built around a fully specified 10-bit 200kSPS (kilo-Sample-Per-Second) general purpose analogue-to-digital converter (ADC). Automatic calibration and self check features ensure accurate and reliable measurements over a temperature range of -40°C to +125°C. The ADC is used to digitize the output of on-chip analog sensors and can also be used to monitor up to 17 external analog inputs for checking environmental aspects of the system performance. System Monitor is fully functional on power up and requires no design effort for basic operation. A complete System Monitor solution is provided by ChipScope™ Pro, CORE Generator™, and ISE™ 9.1i development tools.

Features at a glance:

Single-chip solution for monitoring supply voltages and temperature
On-chip temperature measurement (±4°C)
On-chip power supply measurement (±1%)
Easy to use, self-contained

Usable before, during, and after device configuration
No design required for basic operation
Autonomous monitoring of all on-chip sensors
User programmable alarm thresholds for on-chip sensor

Built-in, user-accessible 10-bit, 200-kSPS (kilosamples per second) ADC

Automatic calibration of offset and gain error
DNL = ±0.9 LSBs maximum

Up to 17 external analog input channels supported

0V to 1V input range
Monitor external sensors e.g., voltage, temperature
General purpose analog inputs

Full access from fabric or JTAG TAP to System Monitor
Fully operational prior to FPGA configuration and during device
power down (access via JTAG TAP only)
Auto chip power down if 125°C is detected on-chip
- Auto power down disabled by default

Table 1. System Monitor Features and Benefits
Feature	Benefit
On-chip temperature measurement	Eliminates need for external thermal diode monitoring IC Guaranteed factory tested accuracy.
On-chip power supply measurement	Eliminates need for external ADC Provides access to power supply measurements inside the package which is not possible with an external ADC
Easy to use	No design work for access to basic thermal and power supply monitoring capability. System Monitor is fully functional on power up without the need to configure the FPGA. Therefore System Monitor is available at all stages during the design cycle.
User accessible ADC	Supports full access to a general purpose ADC. The ADC is fully specified and can be applied to other applications if required.
Self-check and auto calibration	Ensures accuracy over environmental conditions and time
Full access from fabric or JTAG TAP	Provides access to the analog measurements (both on-chip and external) via the JTAG interface, enabling a powerful debug and test tool. The JTAG interface does not require any configuration and it therefore always available. Existing JTAG infrastructure analog measurements can easily be retrieved from difficult to access areas. Boundary scan checks in production can include measurements of voltage, temperature, and other analog quantities.
Fully operational prior to FPGA configuration	Ensures maximum monitoring coverage, since System Monitor is fully functional prior to configuration, during configuration and chip power down. System Monitor can also be used as part of a power on self check during system initialization.
Auto Chip power down	Allows the System Monitor to initiate a chip power down if the on-chip thermal sensor detects a temperature greater than 125°C. This feature can be useful during development or a test with inadequate cooling. An alarm will be issued ~10ms before power down. By default this function is disabled; it must be explicitly enabled by the user.