Sparse Chevron Packaging

      

Best Signal and Power Integrity

Virtex™-5 FPGAs incorporate advanced sparse chevron packaging technology that delivers significant system design benefits to reduce design cycles and system cost. Sparse chevron packaging:

• Reduces inductive crosstalk by providing a low-impedance return path near every I/O pin.
• Reduces the number of external decoupling capacitors, reduces board layer count, and simplifies board design by encapsulating low-inductance, on-substrate bypass capacitors.
• Lowers inductance using continuous Power/GND planes.