Meet performance goals without breaking your power budget

FXT Product List

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Virtex-5 FXT FPGA sample design

Sample Design

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Virtex-5 family brochure

Virtex-5 Family Brochure

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PowerPC 440 processor block

  • Industry-standard architecture
  • 1100 MIPS @ 550 MHz; 2200 DMIPS using a single FPGA with two processors
  • Auxiliary Processor Unit (APU) controller to easily integrate hardware accelerators
  • Crossbar switch for high-throughput 128-bit interfaces and point-to-point connectivity
  • Integrated DMA channels, dedicated memory interface, and Processor Local Bus (PLB) interfaces minimize logic utilization, reduce latency, and optimize performance
  • Simultaneous I/O and memory access maximizes data transfer rates
  • IEEE 754-compatible FPU option for double-/single-precision arithmetic operations

RocketIO™ GTX transceiver

  • Flexible SERDES for multi-rate applications
  • DFE receive equalization for best signal integrity
  • Integrated "gear box" for flexible encoding: 8b/10b, 64b/66b, and 64b/67b
  • Designed to work with integrated PCIe® and Ethernet MAC blocks
  • Less than 200mW power consumption at 6.5 Gbps

550 MHz DSP48E slice

  • 528 GMACS
  • 192 GFLOPS single-precision
  • 68 GFLOPS double-precision
  • DSP system verification accelerated up to 1000x with hardware co-simulation
    (hardware-in-the-loop)

Additional features

Virtex-5 Family for Flexible Platforms: From Simple Logic to Full Systems
System requirements LX LXT SXT FXT
Logic      
High-density ASIC prototyping logic  
General purpose processing
High-performance processing      
Digital signal processing    
Low-power serial I/O    
High-performance serial I/O      
System-on-chip design      
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