What's New in System Generator

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What's New in Service Pack 2 for System Generator 10.1

System Generator Enhancements

Hybrid DCM-CE Support
In the 10.1 release, System Generator introduced a new clocking option to automatically include a DCM (Digital Clock Manager) in a design. This option was limited to designs with no more than three clock rates.

In this release, this clocking option has been enhanced to support designs with more than three clock rates. The additional rates are automatically supported with the CE(Clock Enable) methodology. For example, if a design has six clock rates, the highest three clock rates are supported with a DCM and the lowest three clock rates are supported with the CE methodology.

MATLAB 2008a Support
MATLAB 2008a is now supported by System Generator for DSP

Xilinx DSP Blockset Enhancements

FIR Compiler 4.0
New block now available in System Generator with the following features:

Extended data and coefficient width range up to 49 bits
Polyphase filter bank support for channelizer applications & transpose multiply accumulate architecture
Capability to share control and coefficient memory resources for up to 16 parallel data paths
Virtex-5 and Spartan-3A DSP FPGA family support added for distributed arithmetic architecture.This block supports all the features supported by FIR Compiler LogiCORE v4.0.Divider

Divider Generator 2.0
New block now available in System Generator that generates arithmetic division
algorithms for integer division.

Optional operand widths up to 54 bit wide, synchronous controls, and selectable latency.
Supports Virtex-4, Virtex-5 & Spartan3A-DSP FPGA families for both radix-2 integer division and high-radix division algorithms.

What's New in Service Pack 1 for System Generator 10.1

System Generator Enhancements

Enhanced UCF Support for EDK Import Flow
The handling of UCF (User Constraint File) files in the EDK import flow has been enhanced to support larger UCF file sizes. The UCF file of an imported XPS project is now parsed and modified to form a new UCF file based on the settings of the EDK Processor block. The user has the ability to view and modify the original UCF file and then re-import the XPS project

Enhanced PLB Dual Clock Support
Xilinx Platform Studio projects that use clock generators to drive the PLB bus, MicroBlaze processor and other hardware peripherals with different clocks can now automatically be imported into System Generator for HDL netlisting and hardware co-simulation

Xilinx DSP Blockset Enhancements

CIC Compiler 1.2
Update to existing block

Simulation speedup of ~4x as compared to CIC Compiler 1.1

DDS Compiler 2.1
Update to existing block.

Core generation time has been reduced by ~10x as compared to previous versions of the DDS Compiler
Ability to specify negative frequencies
In the previous version of the DDS Compiler, after reset has been de-asserted, the RDY output goes high 1-cycle too early; this error has been corrected

What's New in System Generator 10.1

System Generator and Project Navigator Integration

System Generator designs can now be more easily incorporated into a larger design inside of Project Navigator by using a new source type in Project Navigator. The System Generator design can also be launched from Project Navigator.

Device Family Support

Virtex®-5 FXT

DCM Support

System Generator now provides the option to automatically include a DCM in the design. Although the optional DCM is abstracted away from the designer, the generated design will leverage DCMs available in the silicon
An alternative option exposes the clock ports at the top level for manual connection to a DCM

Dual Asynchronous-Clock Support for PLB46

This capability gives the designer additional flexibility by allowing the DSP and embedded processing portions of a design to run at different clock rates

Run Time Speed Improvements

Up to two times faster first time initialization of a simulation
Ten times faster initialization when loading the System Generator blockset

M-Based HW Co-Simulation

System Generator models compiled for HW Co-Simulation can now be embedded, configured and used in a MATLAB® M-code script; allowing for calls into hardware to be made from MATLAB

New IP Models Added

FFT 5.0 — Update to existing block which now includes cyclic prefix insertion
FIR Compiler 3.2 — Update that now include support for Virtex-II and Spartan®-3A FPGAs
Reset Generator — New block that produces synchronized downsampled reset signals, which eliminates the need to manually create these signals
CIC 1.1 — New block now available in System Generator

Supported Third-Party Tools

MATLAB 2007a and 2007b
Synplify Pro 8.9
ModelSim 6.3c