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Power Efficiency

Unrivaled System-level Power Reduction

Through careful selection of silicon process and power-conscious architecture design, Xilinx devices deliver power efficiency across all product portfolios, including Spartan-6, 7 series, UltraScale™, and UltraScale+™ FPGAs, and SoCs. With each generation, Xilinx broadens its power reduction capabilities, ranging from process enhancements, architectural innovations, aggressive voltage scaling strategies, and advanced software optimization strategies. More detail on portfolio-specific capabilities, silicon process advantages, and benchmark comparisons are shown below. Power estimation, thermal models, full software support, and demonstration boards are publically available for all families.

UltraScale+ FPGAs

Based on a high performance, low-power semiconductor process (TSMC 16nm FinFET+), the UltraScale+ device families delivers up to 60% overall device-level power savings over 7 series FPGAs and SoCs. Architectural enhancements include:

  • Hardware-based clock gating
  • Hardened BRAM cascading
  • DSP block efficiencies
  • Power-optimized transceivers

Through architectural innovation and a dual-voltage operation of the primary core fabric, UltraScale+ families more than double the performance-per watt-capabilities of 7 series families by realizing power reductions while improving overall performance.

operating-voltage

Zynq UltraScale+ MPSoCs

In addition to all the power reducing capabilities of UltraScale+ FPGA logic, Zynq UltraScale+ MPSoCs utilize multiple power islands and domains within the processing system for coarse-grain and fine-grain dynamic power gating to continually adjust power consumption to performance demands, lowering overall device power.

UltraScale FPGAs

Based on a low-power 20nm semiconductor process coupled with significant static and power gating, UltraScale FPGA families deliver up to 40% overall device-level power savings compared to 7 series FPGAs. Architectural enhancements shared with UltraScale+ devices include

  • Hardware-based clock gating
  • Hardened BRAM cascading
  • DSP block efficiencies
  • Power-optimized transceivers
operating-voltage-2

7 Series FPGAs & Zynq-7000 All Programmable SoCs

As the only 28nm FPGAs and SoCs fabricated on a high-performance, low-power process (28HPL), 7 series devices offer up to 50% total power reduction over previous generation families and superior performance per watt compared to competing 28nm solutions. Architectural and block-level innovations include:

  • Partial reconfiguration for static power savings
  • Multi-mode I/O control
  • Intelligent clock gating
  • Power binning and voltage scaling

View competitive benchmark summaries as well as detailed benchmark process.

Optimized Power Delivery Solutions

Power management requirements are very diverse and often unique to a customer design. As a result, no single power management design can provide the optimal solution. Xilinx partners with the industry’s leading power management companies to provide guidance on the power supply requirements of Xilinx products. These companies include:

Power Management Companies

Distribution Partner

Below you will find a selection of reference designs developed together with some of our power management partners. Designs are grouped by product family, however, many of these reference designs can be easily modified and applied to other product families. Please contact our partners for additional information and guidance in relation to any designs shown below.

Vendor Reference Design Target Device(s)
Texas Instruments 25-30W Remote Radio Head (use-case 2) ZU9EG, ZU15EG

Infineon

UltraZed ZU3 Solution Offering Full Power Management Flexibility (use-case 4)

ZU3CG/EG

Maxim

25-30W Remote Radio Head (use-case 2)

ZU9EG, ZU15EG

Maxim

20W Wireless Backhaul (use-case 2)

ZU9EG, ZU15EG

Note: All solutions are the responsibility of the specific power vendor. Please check with the appropriate power vendor for additional information, e.g., availability.

Tools

Xilinx provides best-in-class tools to estimate pre-implementation power consumption, optimize for lowest power at every design stage, and provide extensive analysis for user-guided optimization. Below are a variety of power-related and Xilinx industry-leading hardware and software-based tools for designers to get started today.