AR #31685 - ChipScope Pro IBERT, Virtex-5 FPGA - How can I use a SYSCLK outside the 50-100 MHz range?

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ChipScope Pro IBERT, Virtex-5 FPGA - How can I use a SYSCLK outside the 50-100 MHz range?

AR# 31685
Part SW-ChipScope IBERT
Last Modified 2009-10-28 00:00:00.0
Status Active
Keywords MGT, GTP, GTX, transceiver, serial, tx, rx, clocking, settings

Description

Keywords: MGT, GTP, GTX, transceiver, serial, tx, rx, clocking, settings

How can I use a SYSCLK outside the 50-100 MHz range?

Solution

To use a SYSCLK outside the required range of IBERT, follow these steps:

Source Files: ftp://ftp.xilinx.com/pub/swhelp/ise10_updates/31685.zip

1. Create your IBERT core using the IBERT CORE Generator with the following differences:
- enter the correct frequency for the userclk, the frequency that is after the DCM/PLL that is going to be added to the design as a clock multiplier or divider.
2. Once the first synthesis process begins, hit the Cancel button and exit the Generator.
3. Go into the project/ibertgtp_temp or project/ibertgtx_temp directly, as applicable.
4. Edit the "ibert_top.v" file.
- The system clock goes into the main ibert module on the DCLK_I port. This connectivity is going to be changed.
- Change the DCLK generation section to add a DCM or PLL to the path, but instead of connecting an internal refclk, use the dclk. See the example attached in the linked ZIP file and below:

/*******************************************************************************
wire dclk_intermediate; -- Add this

* DCLK Generation global buffer
*/
BUFG U_DCLK_BUFG (.I(dclk_in),.O(dclk_intermediate));

PLL_ADV
#(
// Specify your clock period here in NS
.CLKIN1_PERIOD(6.6), // 150 MHz
.CLKFBOUT_MULT(4),
.DIVCLK_DIVIDE(1),


// Choose this number (integer from 1 to 128) to make sure
// the output clock is under 100 MHz
.CLKOUT0_DIVIDE(8)


) pll_refclk (
.CLKIN1(dclk_intermediate),
.CLKIN2(dclk_intermediate),
.CLKINSEL(1'b1),
.CLKFBIN(fbin),
.CLKFBOUT(fbout),
.CLKOUT0(dclk_pll),
.RST(rst),
.LOCKED(lock),
.REL(1'b0),
.CLKOUT1(), .CLKOUT2(), .CLKOUT3(), .CLKOUT4(), .CLKOUT5()
);
// end insert

BUFG U_FB (.I(fbout), .O(fbin));
BUFG U_PLL_BUFG (.I(dclk_pll), .O(dclk));
BUFG U_DCLK_BUFG (.I(dclk_in),.O(dclk));

/*******************************************************************************

5. run "make -f ibert.mak"

 
 
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