AR #33282 - Spartan-6 FPGA - Speed Files Revision History

AR#	33282
Part	SW-Speedfiles
Last Modified	2009-09-15 00:00:00.0
Status	Active
Keywords	changes, updates, new, current, revised, release, speeds, file

Solution

Speed Files Revision History

1.01 Release: Description and Explanation of Changes - 11.3
+ added support for 6slx75(t)
+ DCM - Updated DCM_OFFSET values. This makes the min bigger than the max (on purpose) to prevent negative setup and hold windows on downstream blocks.
+ DSP - For existing paths that use OPMODE6 or generic OPMODEs that include B1REG, a pre-adder delay was added. - There were more parameters that were added to reduce the delay when the pre-adder is specifically turned off.
+ Interconnect - Added new speed models for input path from pad to IOI.
+ PLL - Updated PLL_OFFSET values. This makes the min bigger than the max (on purpose) to prevent negative setup and hold windows on downstream blocks. - Set system synchronous setting set to tap value 0. This was based off silicon characterization.
+ BRAM - Differentiated between setup / hold and recovery / removal checks when in synchronous and asynchronous reset mode.
+ IO / Clocking - Update O_BUFIO2.drive from matching clk tree simulations - Updates to IO and clocking models BSW_IOBUF_MUX,BSW_TERM_CLK,BSW_TERM_CLK2 - Updated B_IOCLK_TB/LR for sa16 and sa45 - Updated BSW_REGC_CLK_MUX_2 from design
+ Updated IOB, clocking components
+ BRAM/DSP - Updated input pin delays
+ GTP - Added data sheet parameters and MINPERIOD values for D_GTPA1_DUAL_{GCLK??,PLLCLK??}_REFCLKPLL
+ PCIe - Updated values for -3 speed grade
+ SERDES - Updated values