| AR# |
33720 |
| Part |
IP-DS-Embedded Tri-Mode EMAC |
| Last Modified |
2009-10-28 00:00:00.0 |
| Status |
Active |
| Keywords |
Virtex-5, TEMAC, tri-speed, patch, installation, instruction, ip0_L, IP Update 1, LXT, SXT, FXT |
Description
Keywords: Virtex-5, TEMAC, tri-speed, patch, installation, instruction, ip0_L, IP Update 1, LXT, SXT, FXT
Offset constraints can be added to the example design UCF file to insure that IDELAY values are set correctly for GMII and RGMII interfaces.
Solution
The following offset constraints can be added to the example design UCF file. The '#' corresponds to EMAC0 or EMAC1.
1) For a GMII interface (non Byte-PHY):
# Identify GMII Rx Pads
INST "gmii_rxd_#<?>" TNM = "gmii_rx_#";
INST "gmii_rx_dv_#" TNM = "gmii_rx_#";
INST "gmii_rx_er_#" TNM = "gmii_rx_#";
# Constrain GMII inputs for 2 ns setup time and 0 ns hold time, with respect
# to rising edge of GMII_RX_CLK_#
TIMEGRP "gmii_rx_#" OFFSET = IN 2 ns VALID 2 ns BEFORE "GMII_RX_CLK_#" RISING;
2) For a Byte-PHY GMII interface:
# Identify GMII Rx Pads
INST "gmii_rxd_#<?>" TNM = "gmii_rx_#";
INST "gmii_rx_dv_#" TNM = "gmii_rx_#";
INST "gmii_rx_er_#" TNM = "gmii_rx_#";
# Constrain GMII inputs for 2 ns setup time and 0 ns hold time, with respect
# to both the rising and falling edges of GMII_RX_CLK_0
TIMEGRP "gmii_rx_#" OFFSET = IN 2 ns VALID 2 ns BEFORE "GMII_RX_CLK_#" RISING;
TIMEGRP "gmii_rx_#" OFFSET = IN 2 ns VALID 2 ns BEFORE "GMII_RX_CLK_#" FALLING;
3) For an RGMII interface:
# Identify RGMII Rx Pads
INST "rgmii_rxd_#<?>" TNM = "rgmii_rx_#";
INST "rgmii_rx_ctl_#" TNM = "rgmii_rx_#";
# Constrain RGMII inputs for 1 ns setup time and 1 ns hold time, with respect
# to both the rising and falling edges of RGMII_RXC_#
TIMEGRP "rgmii_rx_#" OFFSET = IN 1 ns VALID 2 ns BEFORE "rgmii_rxc_#" RISING;
TIMEGRP "rgmii_rx_#" OFFSET = IN 1 ns VALID 2 ns BEFORE "rgmii_rxc_#" FALLING;
The offset constraints may need to be adjusted for particular board and PHY interfaces depending on the clock and data skew coming into the FPGA for a particular system. The IDELAY_VALUEs specified in the UCF file may need to be adjusted for a particular device and pinout. More details on I/O timing and setting IDELAY constraints can be found in the Virtex-5 Embedded Tri-Mode Ethernet MAC Wrapper Getting Started Guide in the Constraining the Example Design Appendix:
http://www.xilinx.com/support/documentation/ip_documentation/v5_emac_gsg340.pdf