Last 7 Days' Answers
AR #15938 - Install - Device Support on Xilinx Design Tools
Last Modified: 2009-11-05 00:00:00.0
AR #18329 - Endpoint for PCI Express - What clock frequency must be used when implementing a PCI Express solution in a Xilinx device?
Last Modified: 2009-10-16 00:00:00.0
AR #23990 - 8.2i MAP - Master Answer Record for MAP Trimming Issues
Last Modified: 2009-11-05 00:00:00.0
AR #31960 - Spartan-3A/-6 Devices - Support of GTLP Input using HSTL Input Buffer
Last Modified: 2009-11-04 00:00:00.0
AR #33312 - Serial RapidIO v5.4 - Release Notes and Known Issues for ISE software 11.3
Last Modified: 2009-11-05 00:00:00.0
AR #33277 - Spartan-6 FPGA Integrated Block Wrapper v1.2 for PCI Express - Release Notes and Known Issues for ISE Design Suite 11.3
Last Modified: 2009-11-05 00:00:00.0
AR #33454 - Serial RapidIO v5.4 - Virtex-6 FPGA hardware validation updates
Last Modified: 2009-11-03 00:00:00.0
AR #33741 - MIG v3.2, Virtex-4/Virtex-5 FPGA DDR/DDR2 - The timing spreadsheet provided to calculate timing margin before and after DQS incorrectly only accounts for Tstaphaoffset in the "Before DQS" column
Last Modified: 2009-11-05 00:00:00.0
AR #33756 - ISE software 11 - buffer_type in the UCF not supported for AUTOBUF starting in 11.4
Last Modified: 2009-11-05 00:00:00.0
AR #33728 - ISE Software 11.3 Licensing - Free, licensed IP cores fail to generate or implement - No license for component <IP coren name> found
Last Modified: 2009-11-05 00:00:00.0
AR #33757 - HW SelectIO technology - Implementation tools do not allow I/O pins with the I/O standard SSTL2_II to be assigned to Spartan-6 FPGA Bank 0 or Bank 2
Last Modified: 2009-11-05 00:00:00.0
AR #33736 - Distributed Memory Generator v4.2 - Pipeline stages reset to zero when core is generated
Last Modified: 2009-11-05 00:00:00.0
AR #33737 - Distributed Memory Generator v4.2 - Reset and CE options not enabled in the GUI
Last Modified: 2009-11-05 00:00:00.0
AR #33603 - LogiCORE 3GPP LTE MIMO Encoder v2.0 - Are there any examples for how the core is used?
Last Modified: 2009-11-05 00:00:00.0
AR #33761 - Spartan-6 FPGA Integrated Block Wrapper v1.2 for PCI Express - How to Enable use of a 100 MHz Reference Clock
Last Modified: 2009-11-05 00:00:00.0
AR #32827 - 11.2 iMPACT - Virtex-6 FPGA Indirect BPI Programming support
Last Modified: 2009-11-04 00:00:00.0
AR #32656 - ISE Design Suite 11 ChipScope Pro Analyzer Update 2 (11.3) - README
Last Modified: 2009-11-04 00:00:00.0
AR #33752 - 11.3 BitGen - The TIMER value setting does not work
Last Modified: 2009-11-04 00:00:00.0
AR #33754 - 11.3 ChipScope Pro - Number of ATD pins available on ATC2 core does not match with the User Guide
Last Modified: 2009-11-04 00:00:00.0
AR #33755 - 11.x ChipScope Pro Inserter - Spartan-6 is shown as the device family when the project is Automotive or Low Power Spartan-6 FPGA
Last Modified: 2009-11-04 00:00:00.0
AR #29393 - Spartan-3A DSP FPGA - Speed Files Revision History
Last Modified: 2009-11-03 00:00:00.0
AR #33740 - 11.3 Spartan-6/Virtex-6 FPGA MAP - IODELAYs are being auto-inserted for some paths in ISE software version 11.3 where they did not in 11.2.
Last Modified: 2009-11-03 00:00:00.0
AR #33743 - 11.3 Virtex-6 FPGA MAP - Change in trimming behavior related to IBUFDS_GTXE1 components
Last Modified: 2009-11-03 00:00:00.0
AR #33744 - 11.3 Virtex-5 FPGA MAP - Logic corruption related to combination of Global Opt options
Last Modified: 2009-11-03 00:00:00.0
AR #33745 - ChipScope Pro Analyzer - ERROR: Failed to open Xilinx Platform USB Cable. See message(s) above
Last Modified: 2009-11-03 00:00:00.0
AR #20953 - Virtex-4 - Speed File Revision History
Last Modified: 2009-11-02 00:00:00.0
AR #33281 - Virtex-6 FPGA - Speeds Files Revision History
Last Modified: 2009-08-19 00:00:00.0
AR #33282 - Spartan-6 FPGA - Speed Files Revision History
Last Modified: 2009-09-15 00:00:00.0
AR #33626 - Spartan-6 FPGA GTP Transceiver Wizard v1.3 - Example design ChipScope tool ILA core reports incorrect behavior
Last Modified: 2009-11-02 00:00:00.0
AR #33666 - 11.1 Licensing - ML507 Embedded Edition tools do not contain ISE software license
Last Modified: 2009-11-02 00:00:00.0
AR #12592 - 11 EDK - Spaces are not allowed in installation directory paths
Last Modified: 2009-10-30 00:00:00.0
AR #20708 - 11.1 CORE Generator - Receiving error messages "Could not reserve enough space for object heap" and "Could not create the Java virtual machine"
Last Modified: 2009-10-30 00:00:00.0
AR #33016 - Spartan-6 FPGA Clocking - DCM de-skew calculations incorrect
Last Modified: 2009-10-30 00:00:00.0
AR #32389 - 11.1 ISE Design Suite Install - XilinxUpdate only works on the last set installed tools
Last Modified: 2009-10-30 00:00:00.0
AR #33187 - 11.3 ISE Design Suite XilinxUpdate - Can I run XilinxUpdate in silent (batch) mode?
Last Modified: 2009-10-30 00:00:00.0
AR #33422 - ISE Simulator (ISim) - Error "tracing limit is reached. Signal tracing will stop!"
Last Modified: 2009-10-30 00:00:00.0
AR #33423 - ISE Simulator (ISim) - Error "Simulator is abnormally terminated"
Last Modified: 2009-10-30 00:00:00.0
AR #33381 - ISE Design Suite 11 - ISE Simulator (ISim) Known Issues
Last Modified: 2009-10-30 00:00:00.0
AR #33727 - ISE Simulator (ISim) - HDLCompiler:1044 - "Unknown" Line 0: /data/Xilinx/11.1/ISE/verilog/hdp/lin64/xip/ ..."
Last Modified: 2009-10-30 00:00:00.0
AR #33729 - ISE Simulator (ISim) - Pressing the Sync Time button makes signals in the Wave window disappear
Last Modified: 2009-10-30 00:00:00.0
AR #33730 - ISE Simulator (ISim) - "ERROR:HDLCompiler:597 when attempting to pass multiple generics in simulation"
Last Modified: 2009-10-30 00:00:00.0
AR #33732 - ISE Simulator (ISim) - $fscanf does not return "-1" upon EOF (end of file)
Last Modified: 2009-10-30 00:00:00.0