Yesterday's Answers
AR #20093 - 6.3is1 PAR - "ERROR:Place:120 - There were not enough sites to place all selected components"
Last Modified: 2008-09-04 00:00:00.0
AR #21066 - Virtex-4 XtremeDSP Slice - When do I need to set the LEGACY_MODE for the DSP48?
Last Modified: 2008-09-04 00:00:00.0
AR #21911 - Virtex-4 XtremeDSP Slice and MAP 7.1.03i - Why are the clock enables on my XtremeDSP Slice (DSP48) being disabled? Why is there no output from my XtremeDSP Slice (DSP48), or why is the POUT zero?
Last Modified: 2008-09-04 00:00:00.0
AR #22598 - 8.1i Architecture Wizard, XtremeDSP Slice - What bits does the multiplier output when full precision is not used on the output?
Last Modified: 2008-09-04 00:00:00.0
AR #25096 - Spartan-3A DSP FPGA-DSP48 - Why does the Spartan-3A HDL Libraries Guide not have an instantiation template for the DSP48A in the ISE 9.1.03i release?
Last Modified: 2008-09-04 00:00:00.0
AR #25428 - Architecture Wizard, XtremeDSP Slice - Why does the Adder/Subtractor Architecture Wizard always have a clock input, even when no registers are selected, or why is ACASCREG or MREG always set to '1' in the HDL?
Last Modified: 2008-09-04 00:00:00.0
AR #29976 - LogiCORE DDS (Direct Digital Synthesizer) Compiler - Release Notes and Known issues
Last Modified: 2008-09-04 00:00:00.0
AR #30663 - 10.1 ISE - The Project Navigator Cleanup Project File process deletes NGC and EDN files manually copied to the project directory
Last Modified: 2008-08-01 00:00:00.0
AR #30835 - 10.1 EDK, ppc440mc_ddr2 - Incorrect write data during write transactions, under certain voltage and temperature conditions
Last Modified: 2008-09-04 00:00:00.0
AR #31168 - 10.1.01 ISE - View HDL instantiation Template results in ERROR:HDLParsers:3264 - Can't read file "/../..clock_source2.vhd" (...)
Last Modified: 2008-08-26 00:00:00.0
AR #31286 - 10.1 EDK, MPMC v4.02.a - "ERROR:ConstraintSystem:58 - Constraint does not match any design objects"
Last Modified: 2008-09-04 00:00:00.0
AR #31299 - MIG v2.2, Virtex-5 DDR2 SDRAM - Timing parameters are incorrect in simulation and hardware
Last Modified: 2008-09-04 00:00:00.0
AR #30933 - 10.1 EDK, MPMC v4.01.a - DM-Pins always High and DQ incorrect on writes when using SDR SDRAM PHY
Last Modified: 2008-09-04 00:00:00.0
AR #31446 - 10.1 EDK, ppc440mc_ddr2 - How do I use the ppc440mc_ddr2 signal MI_MCCLKDIV2?
Last Modified: 2008-09-04 00:00:00.0
AR #31447 - 10.1 EDK, ppc440mc_ddr2 - Does the MI_MCRESET signal need to be an external input?
Last Modified: 2008-09-04 00:00:00.0
AR #31449 - 10.1 EDK, ppc440mc_ddr2 - tRFC is violated during calibration
Last Modified: 2008-09-04 00:00:00.0
AR #31450 - 10.1 EDK, ppc440mc_ddr2 - Calibration hangs in stage 3 during simulation
Last Modified: 2008-09-04 00:00:00.0
AR #31533 - 10.1 Partitions - Non-deterministic results seen between different operating systems
Last Modified: 2008-09-04 00:00:00.0
AR #31592 - 10.1 Floorplan Editor - Image of Spartan-3 Generation in TQ144 Package is incorrect
Last Modified: 2008-09-04 00:00:00.0
AR #31593 - 10.1 PlanAhead - How do I run the launch scripts created by ExploreAhead in a different OS than the one in which I created the scripts?
Last Modified: 2008-09-04 00:00:00.0
AR #31603 - 10.1 Virtex-5 MAP - "INTERNAL_ERROR:Pack:pktbaplacepacker.c:897:1.139.4.6 - Unable to obey placement request which requires the combination ..."
Last Modified: 2008-09-04 00:00:00.0
AR #31607 - 10.1 EDK - Does Xilkernel support the FPU core design for the Power PC 405 and Power PC 440?
Last Modified: 2008-09-04 00:00:00.0
AR #31608 - LogiCORE DDS (Direct Digital Synthesizer) Compiler - The output frequency range on page 3 of the GUI is greater than should be allowed according to my clock frequency
Last Modified: 2008-09-04 00:00:00.0
AR #31536 - Architecture Wizard, XtremeDSP Slice - Why is there no option to select the BCascade Out Pipeline, when using the Multiply Accumulate (MACC) Architecture Wizard?
Last Modified: 2008-09-04 00:00:00.0
AR #31609 - 9.1i EDK, plb_ddr - PLB_DDR controller C_NUM_BANKS_MEM actually refers to rank number
Last Modified: 2008-09-04 00:00:00.0
AR #31610 - Architecture Wizard, XtremeDSP Slice - Why does the Multiplier or Multiply Accumulate (MACC) Architecture Wizard always have a clock input, even when no registers are selected, or why is ACASCREG or MREG always set to '1' in the HDL?
Last Modified: 2008-09-04 00:00:00.0
AR #31611 - Architecture Wizard, XtremeDSP Slice - Why does the Accumulator or Multiply Accumulate (MACC) Architecture Wizard select the wrong enables, when only one level of pipelining is selected for the A and B registers?
Last Modified: 2008-09-04 00:00:00.0