Yesterday's Answers
AR #15938 - Install - Device Support on Xilinx Design Tools
Last Modified: 2009-11-05 00:00:00.0
AR #18329 - Endpoint for PCI Express - What clock frequency must be used when implementing a PCI Express solution in a Xilinx device?
Last Modified: 2009-10-16 00:00:00.0
AR #23990 - 8.2i MAP - Master Answer Record for MAP Trimming Issues
Last Modified: 2009-11-05 00:00:00.0
AR #31960 - Spartan-3A/-6 Devices - Support of GTLP Input using HSTL Input Buffer
Last Modified: 2009-11-04 00:00:00.0
AR #33312 - Serial RapidIO v5.4 - Release Notes and Known Issues for ISE software 11.3
Last Modified: 2009-11-05 00:00:00.0
AR #33277 - Spartan-6 FPGA Integrated Block Wrapper v1.2 for PCI Express - Release Notes and Known Issues for ISE Design Suite 11.3
Last Modified: 2009-11-05 00:00:00.0
AR #33454 - Serial RapidIO v5.4 - Virtex-6 FPGA hardware validation updates
Last Modified: 2009-11-03 00:00:00.0
AR #33741 - MIG v3.2, Virtex-4/Virtex-5 FPGA DDR/DDR2 - The timing spreadsheet provided to calculate timing margin before and after DQS incorrectly only accounts for Tstaphaoffset in the "Before DQS" column
Last Modified: 2009-11-05 00:00:00.0
AR #33756 - ISE software 11 - buffer_type in the UCF not supported for AUTOBUF starting in 11.4
Last Modified: 2009-11-05 00:00:00.0
AR #33728 - ISE Software 11.3 Licensing - Free, licensed IP cores fail to generate or implement - No license for component <IP coren name> found
Last Modified: 2009-11-05 00:00:00.0
AR #33757 - HW SelectIO technology - Implementation tools do not allow I/O pins with the I/O standard SSTL2_II to be assigned to Spartan-6 FPGA Bank 0 or Bank 2
Last Modified: 2009-11-05 00:00:00.0
AR #33736 - Distributed Memory Generator v4.2 - Pipeline stages reset to zero when core is generated
Last Modified: 2009-11-05 00:00:00.0
AR #33737 - Distributed Memory Generator v4.2 - Reset and CE options not enabled in the GUI
Last Modified: 2009-11-05 00:00:00.0
AR #33603 - LogiCORE 3GPP LTE MIMO Encoder v2.0 - Are there any examples for how the core is used?
Last Modified: 2009-11-05 00:00:00.0
AR #33761 - Spartan-6 FPGA Integrated Block Wrapper v1.2 for PCI Express - How to Enable use of a 100 MHz Reference Clock
Last Modified: 2009-11-05 00:00:00.0