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UltraScale and UltraScale+ GTH Transceivers

Getting StartedDesign ResourcesSupport ResourcesTransceiver IP Resources

Refer to the High Speed Serial Product Page for more information on Xilinx GTY Transceivers.

High-Speed Serial I/O Designer's GuideDate
 Basic Concepts 
 Purpose of SERDES 
 History of SERDES 
 Alignment, Encoding, Emphasis, Buffers, Channel Bonding and Clock Correction 
UltraScale GTH Transceivers User GuideDate
 RX Byte and Word Alignment08/15/2018
 RX 8B/10B Decoder08/15/2018
 Buffer Control08/15/2018
 RX Clock Correction08/15/2018
 RX Channel Bonding08/15/2018
 RX Synchronous Gearbox08/15/2018
 RX Clock Data Recovery (CDR)08/15/2018

Product Specifications

Product Specifications

The characterization reports for UltraScale and UltraScale+ devices are confidential. Please contact a Xilinx Specialist for more information.

Supported ProtocolsDate
 Virtex UltraScale - GTH Transceiver Protocol List10/30/2018
 Kintex UltraScale - GTH Transceiver Protocol List10/30/2018
Max Data RatesDate
 Virtex UltraScale - GTH Transceiver Performance10/30/2018
 Kintex UltraScale - GTH Transceiver Performance10/30/2018

UltraScale Transceiver Wizard

UltraScale Transceiver Wizard

Refer to the UltraScale FPGAs Transceivers Wizard IP Product Page for more information regarding this IP.

Using the Wizard IP CoreDate
 UltraScale Transceiver Wizard - Release Notes and Known Issues09/24/2018
 Overview04/04/2018
 Designing with the Core04/04/2018
 Design Flow Steps04/04/2018
 Example Design04/04/2018
 Test Bench Usage04/04/2018

Understanding GT Transceiver Features

Understanding GT Transceiver Features

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