Processor Core Application Notes

This document details the VHDL implementation of an I2C controller in a Xilinx CoolRunner XPLA3 256 macrocell CPLD. CoolRunner CPLDs are the lowest power CPLDs available, making this the perfect target device for an I2C controller.

MicroBlaze™ has the ability to use its dedicated FSL bus interface to integrate a customized IP core into a MicroBlaze soft processor-based system. This document describes possible methods to include customized IP cores into an SCP-based design.

XAPP482 describes a working MicroBlaze™ system that stores software code, user data, and configuration data in non-volatile Platform Flash PROMs, simplifying system design and reducing cost. It provides a portable hardware design, software design, and additional script utilities to be used during the implementation flow.

The Constant (k) Coded Programmable State Machine (KCPSM) presented in this application note is a fully embedded 8-bit microcontroller macro for the Virtex™ and Spartan™-II devices. The module is remarkably small at just 35 CLBs, less than half of the smallest Spartan™ XC2S15 device, and virtually free in an XCV2000 device by consuming less than 0.37% of the device CLB.

This application note discusses the use of Xilinx XMD and GNU to debug software defects.

This application note describes how to properly setup external and internal interrupts in an embedded hardware system. Use of an interrupt controller to manage more than one interrupt will also be included.

This application note describes the steps for configuring the processor caches using the USR_ACCESS Register.

In embedded systems, designers can reduce component count and increase flexibility by using a microprocessor to configure an FPGA. C code illustrates the use of either Slave Serial or SelectMAP mode. CPLD design files illustrate a synchronous interface between processor and FPGA.

The inclusion of embedded processor cores in Xilinx FPGAs opens new doors for high-throughput digital signal processing applications. System Generator for DSP is a high-level modeling environment for designing custom DSP data paths with performance and efficiency comparable to hand-crafted designs. Because System Generator for DSP is tightly integrated with the Simulink® and MATHLAB® tools from The Mathworks, Inc., FPGA designs are implemented by users in a familiar setting without being overly concerned with underlying hardware details.

This application note describes how C-to-HDL tools can easily create a hardware coprocessor from a critical function in the software system. The Auxiliary Processor Unit (APU) controller closely couples the embedded PowerPC™ processor and the Fabric Coprocessor Module (FCM), and provides a low-latency, high-bandwidth communication path. This application note demonstrates an accelerated Mandelbrot image generation application by moving computation-intensive functions to the hardware domain and attaching it to the PowerPC processor using the Virtex™-4 FX APU controller.

The DEBUGHALT controller is a small, yet versatile piece of FPGA logic that simplifies the startup process of the PowerPC™ 405 (PPC405) processors in systems that cannot have any memory at the reset vector, or in systems that completely run out of cache. This application note is accompanied by a reference design that demonstrates debug halt mode implemented in the embedded PPC405 processor available on Virtex-II Pro™ FPGAs. The DEBUGHALT controller design enables external control of the PPC405 processor through the JTAG interfa

This application note describes the implementation of a processor lockstep system using embedded PowerPC™ 405 (PPC405) processors in Xilinx Virtex™-II Pro FPGAs, along with Xilinx software tools. To verify lockstep functionality, users learn how to build and run the Linux operating system with the MontaVista Linux Preview Kit and also how to probe signals in the lockstep system with Xilinx ChipScope™ Pro tools.

Describes how to implement a Virtex™-4 FX PowerPC™ 405 system with the Xilinx floating point unit (FPU) coprocessor.

UltraController-II is a minimal footprint embedded processing engine based on the PowerPC™ 405 (PPC405) processor core embedded within Virtex™-4 and Virtex-II Pro Platform FPGAs. System designers can easily incorporate the UltraController-II black-box processing engine into larger ISE designs to gain additional degrees of freedom by balancing usage of the high-performance FPGA fabric with the algorithmic flexibility of software.

The embedded PowerPC™ 405 processor blocks in Virtex-II Pro™ devices with –7 speed grades can achieve speeds to 400 MHz. Special considerations are necessary when using the left processor in dual-processor devices. This application note describes these considerations and provides a necessary macro when operating the left processor at speeds greater than 350 MHz.

This is the Xilinx Dual Processor Reference Design suite that accompanies XAPP996 and WP262.

This application note describes an embedded Simple Mail Transfer Protocol (SMTP) client reference design that demonstrates the capacity of a network-enabled embedded system to report on its status via E-mail. It describes how to set up the Platform Studio design environment for the PowerPC™ 405, configure the 10/100 Ethernet MAC core, and create the Board Support Package (BSP) for VxWorks®.

The Gigabit System Reference Design (GSRD) leverages the techniques outlined in Xilinx application note XAPP535 to demonstrate a high-performance Gigabit Ethernet reference system using a Xilinx Virtex-II Pro FPGA.

This application note introduces two key technologies from the Gigabit System Reference Design (GSRD): the Multi-Port Memory Controller (MPMC), which allows multiple entities to directly access memory bypassing a system bus, and the Communication Direct Memory Access Controller (CDMAC), which works with the MPMC to provide multiple channels of Direct Memory Access (DMA) for communication style devices.

This application note describes the implementation of an 8-bit microcontroller design using a CoolRunner™-II CPLD. The PicoBlaze™ Microcontoller instructions can be customized to make an application-specific microcontroller. CoolRunner-II devices, the latest CPLD family from Xilinx® offers both low power and high-speed performance. A complete VHDL code for PicoBlaze microcontroller design and C code for its assembler are available with this application note.

The Xilinx high-performance CPLD, FPGA, and configuration PROM families provide in-system programmability, reliable pin locking, and JTAG boundary-scan test capability. This powerful combination of features allows designers to make significant changes and still keep the original device pin-outs, which eliminates the need to re-tool PC boards.

This application note describes the embedded PowerPC™ 405 (PPC405) processor in the Virtex™-4 FX FPGA and the main features of an APU-enhanced system. It includes examples illustrating the APU transfers data between the processor and the FPGA.

The UltraController™ embedded processor is a complete reference design of a "lightweight" PowerPC™ microcontroler. A 32-bit I/O design is a simple block for integration into larger designs. It only requires a reset and clock input. The UltraController solution utilizes the available PowerPC processor(s) in the Virtex-II Pro™ device and several block RAMs. The UltraController design is available for a variety of applications including logic and data control, device configuration, system monitoring, and simple data manipulation.

The PicoBlaze™ module is a fully embedded 8-bit microcontroller macro for the Virtex™-II series. Although it could be used for processing of data, the PicoBlaze™ macro is most likely to be employed in applications requiring a complex, but non-time-critical state machine.

This application note illustrates how to simulate PowerPC 440 systems.