Configuration PROMs

This application note outlines how to successfully configure a Spartan™-3A FPGA from a Platform Flash PROM. Including hardware requirements and software flows for generating and programming PROM files.

This application note describes a low-profile In-System Programming solution, consisting of HDL IP and Xilinx® software tools, designed to handle only the JTAG functions needed for programming; resulting in less logic required and a smaller programming file compared to other full-featured solutions.

This application note describes how to indirectly program an SPI Serial Flash PROM through the JTAG interface of a Spartan™-3A FPGA using iMPACT 9.1.01i. The hardware setup, software flows for file generation, and programming are also covered.

This application note describes how to indirectly program select BPI PROMs through the JTAG interface of a Virtex™-5 FPGA using iMPACT. The required hardware setup, BPI-UP PROM file generation, and the indirect programming flow are described.

This application note discusses the Serial Peripheral Interface (SPI) configuration mode introduced in the Virtex™-5 and Spartan™-3E FPGA families. The ISE™ iMPACT in-system programming solution with the Xilinx cables for prototype designs is described.

This application note describes how to retrieve user-defined data from Xilinx configuration PROMs (XC18V00 and Platform Flash devices) after the same PROM has configured the FPGA. The method to add user-defined data to the configuration PROM file is also discussed.

This application note describes a method for the reading and limited writing of small amounts of general-purpose user data into a Xilinx Platform Flash XCF02S (2 Mbit) or XCF04S (4 Mbit) configuration PROM.

This application note discusses the configuration and programming options for Xilinx Complex Programmable Logic Device (CPLD), Field Programmable Gate Array (FPGA), and PROM families and demonstrates some of the most popular configuration methods used for each family. This document includes configuration quick start guidelines for the Virtex™, Spartan™, XPLA3, XC9500, and XC18V00 families.

This Application Note describes the feature of Platform Flash PROMs that allows the user to Multiple-Boot or dynamically reconfigure from up to four Design Revisions.

XAPP482 describes a working MicroBlaze™ system that stores software code, user data, and configuration data in non-volatile Platform Flash PROMs, simplifying system design and reducing cost. It provides a portable hardware design, software design, and additional script utilities to be used during the implementation flow.

This application note contains a reference design consisting of HDL IP and Xilinx® Advanced Configuration Environment (ACE) software utilities that give designers great flexibility in creating in-system programming (ISP) solutions.

The compatibility between the XC1700™ and XC18V00™ series of PROMs allows an engineer to take advantage of the in-system reprogramming features of the XC18V00 PROM during the development phase of a project and the lower cost benefit of an XC1700 series PROM during the production phase of a project. This application note discusses the considerations for systems that support a migration path from the XC18V00 PROM to an XC1700 series PROM. The topics include package compatibility, pin compatibility, I/O voltage compatibility, power and ground connections, and boundary-scan chain integrity.

The Xilinx high-performance CPLD, FPGA, and configuration PROM families provide in-system programmability, reliable pin locking, and JTAG boundary-scan test capability. This powerful combination of features allows designers to make significant changes and still keep the original device pin-outs, which eliminates the need to re-tool PC boards.

Most Xilinx CPLDs, PROMs, and FPGAs have an IEEE Standard 1149.1 (JTAG) port. Xilinx devices with a JTAG port are in-system programmable (ISP) through the JTAG port. The ISP feature is beneficial for fast prototype development. This application note describes a short list of considerations needed to get the best performance from your ISP designs.