Endpoint for PCI Express (Soft-IP)

This is the getting started guide for the LogiCORE Endpoint v3.6 for PCI Express core.

This is the data sheet for the Endpoint v3.6 for PCI Express core.

This application note discusses using the provided Memory Endpoint Test (MET) demonstration driver to exercise the Programmed Input/Output (PIO) design that is delivered with the Endpoint Block Plus Wrapper, Endpoint, and Endpoint PIPE for PCI Express® Xilinx solutions.

This document provides information for debugging board level problems by using ChipScope™ Pro with Endpoint for PCI Express designs using Virtex™-4, Virtex-5, Virtex-II Pro FPGAs, the Endpoint PIPE for PCIe core using Spartan™-3/-3E/-3A FPGAs, and in the Endpoint Block Plus for PCIe core with Virtex-5 devices.

This LogiCORE™ IP Endpoint for PCI Express® User Guide describes the function and operation of the Endpoint solutions for PCI Express, including how to design, customize, and implement the core.

This guide describes these solutions to help designers understand which solutions are available through PCI Express® for each FPGA.