Endpoint Block Plus Wrapper for PCI Express

The LogiCORE™ IP Endpoint Block Plus for PCI Express® core is a high-bandwidth, scalable, and reliable serial interconnect building block for use with Virtex®-5 LXT/SXT/FXT FPGA devices.

The LogiCORE™ IP Endpoint Block Plus for PCI Express® User Guide describes the function and operation of the core, including how to design, customize, and implement the core.

The LogiCORE™ IP Endpoint Block Plus for PCI Express® Getting Started Guide provides information about generating the core using the provided example design, and running the design files through implementation using the Xilinx® tools.

This application note discusses using the provided Memory Endpoint Test (MET) demonstration driver to exercise the Programmed Input/Output (PIO) design that is delivered with the Endpoint Block Plus Wrapper, Endpoint, and Endpoint PIPE for PCI Express® Xilinx solutions.

This document provides information for debugging board level problems by using ChipScope™ Pro with Endpoint for PCI Express designs using Virtex™-4, Virtex-5, Virtex-II Pro FPGAs, the Endpoint PIPE for PCIe core using Spartan™-3/-3E/-3A FPGAs, and in the Endpoint Block Plus for PCIe core with Virtex-5 devices.

This guide describes these solutions to help designers understand which solutions are available through PCI Express® for each FPGA.

This white paper explores the factors of PCI Express® technology and how they affect the performance of a system. This document also provides performance results from two systems that use the Xilinx® Endpoint Block Plus Wrapper for PCI Express in the Virtex®-5 FPGA Integrated Endpoint Block for PCI Express designs.

This application note discusses how to design and implement a Bus Master Direct Memory Access (DMA) design for the Endpoint Block Plus Wrapper Core for PCI Express® using the Virtex®-5 FPGA Integrated Block for PCI Express.