SPI-4 Phase 2 Interface Solutions

This is the Data Sheet for the SPI-4.3 Lite v4.3 core

This is the data sheet for the SPI-4.2 Core v6.3 core.

The LogiCORE™ IP SPI-4.2 Getting Started Guide provides information about customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx tools.

The LogiCORE™ IP SPI-4.2 (PL4) core implements and is fully compliant with the OIF-SPI4-02.1 System Packet Interface Phase 2 standard. Optimized for all Virtex™-5 and Virtex-4 devices, this fully verified solution interconnects physical-layer devices to link-layer devices in 10 Gbps POS, ATM, and Ethernet applications.

This guide introduces the SPI-4.2 core and provides basic information for configuring and testing a design targeting only Virtex™-II and Virtex-II Pro FPGA designs.

This user guide describes the function and operation of the Xilinx LogiCORE™ SPI-4.2 (PL4) Lite core, and provides information about designing, customizing, and implementing the core.

This guide provides information about generating the SPI-4.2 (PL4) Lite core, customizing and simulating the core using the provided example design, and running the design files through implementation using Xilinx® tools.