ML450

Describes the components and operation of the ML450 Bit Error Rate Tester (BERT) and its graphical user interface (GUI).

User Guide for the Virtex™-4 ML450 Development Board.

This is the PDF for the ML450 schematics. The schematic source files (Viewdraw) and other related ML450 board files are listed below.

16 channel, LVDS, 4:1 Deserialization, SDR. This design demonstrates the operation of an SFI-4 physical interface in Virtex-4 at the key SFI-4 rates of 622, 644, and 700 Mbits/s. The source synchronous alignment scheme used is bus alignment, meaning that all 16 data channels are treated as one channel and aligned at the same time. This assumes minimal skew between channels. There is no training pattern for this design.

16 Channel, LVDS, 4:1 Deserialization, DDR. This design demonstrates the operation of an implementation similar to SPI-4.2 in Virtex-4. The source synchronous alignment scheme used is bit alignment, meaning that all 16 data channels are treated independently in the alignment process. The alignment in this demo is driven by the XAPP700 reference design. The training pattern is 1111_1111_1100_0000_0000.