Spartan-3

This document provides an overview of all Xilinx memory interface application notes that support Virtex™ Series FPGAs. In addition, some key features of the prevalent memory technologies are also provided. For each application note, the data capture technique, clocking scheme, FPGA resources used, and supported memory technology are described briefly.

This application note describes a method to configure Xilinx FPGAs, such as Spartan®-IIE and Spartan-3 FPGAs, using inexpensive small Serial Peripheral Interface (SPI) flash memories.

This application note describes a cost-optimized copy protection scheme that helps protect an FPGA against cloning. The design leverages an external secure serial EEPROM. The included reference design uses an optimized PicoBlaze™ 8-bit microcontroller. This application note provides a hardware design with associated PicoBlaze software code. The code loads a secret key into the secure EEPROM and authenticates the user system with the secure EEPROM.

This application note describes how to connect a high-speed Texas Instruments (TI) ADS5273 analog-to-digital converter (ADC) with serialized LVDS output to a Virtex™-II or Virtex™-II Pro FPGA. Lower speed ADC devices from this family can be connected to Spartan™-3 FPGAs.

This application note shows the connection of Xilinx® FPGAs to a Texas Instruments™ S320C6000 series Digital Signal Processor (DSP) using the available External Memory Interface (EMIF).

This application note describes a reference design of multi-channel digital up converters(DUCs) and digital down converters (DDCs) for CDMA2000 and UMTS base stations. The provided DSP algorithms meet base station specifications using digital-to-analog conversion rates of 61.44 MHz. Four-channel implementations are described that efficiently map the DSP algorithms into the resources of the Spartan™-3 family of FPGAs.

The Cyclic Redundancy Check (CRC) is a powerful technique to obtain data reliability. This application note discusses the implementation of Configurable CRC Modules with LocalLink interfaces. The user can tailor the features of these modules to suit the protocol or application that is implemented in their system. The user-specified options for each of the configurable features are input parameters to the VHDL code for the modules.

This application note explains how to use the Xilinx Viterbi Decoder LogiCORE™ module (version 5.0 or later) to implement both trellis termination and tail biting.

MicroBlaze™ has the ability to use its dedicated FSL bus interface to integrate a customized IP core into a MicroBlaze soft processor-based system. This document describes possible methods to include customized IP cores into an SCP-based design.

This application note provides users with a general understanding of the SVF and XSVF file formats as they apply to Xilinx devices. Some familiarity with IEEE STD 1149.1 (JTAG) is assumed. For information on using Serial Vector Format (SVF) and Xilinx Serial Vector Format (XSVF) files in embedded programming applications, refer to Xilinx Application Note XAPP058.

This application note discusses the configuration and programming options for Xilinx Complex Programmable Logic Device (CPLD), Field Programmable Gate Array (FPGA), and PROM families and demonstrates some of the most popular configuration methods used for each family. This document includes configuration quick start guidelines for the Virtex™, Spartan™, XPLA3, XC9500, and XC18V00 families.

The J Drive programming engine provides immediate and direct in-system configuration (ISC) support for IEEE Standard 1532 programmable logic devices (PLDs). To configure an in-system device, the programming engine uses the configuration algorithm information from a 1532 Boundary Scan Description Language (BSDL) file to apply configuration data from the 1532 data file through the IEEE Standard 1149.1 test access port (TAP). The J Drive executable, source code, and a programming example are available in a download package from the Xilinx website. The J Drive programming engine can be used for the following Xilinx families: CoolRunner-II CPLDs, XC9500/XL/XV CPLDs, Spartan-3 Generation FPGAs, and Virtex-II (and later) series FPGAs.

Differential signals, such as LVDS or LVPECL, can be difficult to route on simple, four-layer or six-layer PCBs without excessive use of vias. This application note shows how Spartan™-3 Generation FPGAs, with just the inclusion of an inverter in the datapath, can avoid excessive use of vias and fix accidental PCB trace swapping without requiring a PCB respin.

XAPP482 describes a working MicroBlaze™ system that stores software code, user data, and configuration data in non-volatile Platform Flash PROMs, simplifying system design and reducing cost. It provides a portable hardware design, software design, and additional script utilities to be used during the implementation flow.

For the latest version of this application note, see the BSDL chapter in User Guide UG331, Spartan™-3 Generation FPGA User Guide.

For the latest version of this application note, see the IBIS chapter in User Guide UG331, Spartan™-3 Generation FPGA User Guide.

For the latest version of this application note, see the IP Cores chapter in User Guide UG331, Spartan™-3 Generation FPGA User Guide.

For the latest version of this application note, see the Design Tools chapter in User Guide UG331, Spartan™-3 Generation FPGA User Guide.

Describes the multipliers in the original Spartan™-3 FPGA architecture. For the Spartan-3E/-3A FPGA families, see the Multipliers chapter in User Guide UG331, Spartan-3 Generation FPGA User Guide.

For the latest version of this application note, see the Multiplexers chapter in User Guide UG331, Spartan™-3 Generation FPGA User Guide.

For the latest version of this application note, see the SRL16 chapter in User Guide UG331, Spartan™-3 Generation FPGA User Guide.

For the latest version of this application note, see the Distributed RAM chapter in User Guide UG331, Spartan™-3 Generation FPGA User Guide.

For the latest version of this application note, see the Block RAM chapter in User Guide UG331, Spartan™-3 Generation FPGA User Guide.

For the latest version of this application note, see the DCM chapter in User Guide UG331, Spartan™-3 Generation FPGA User Guide.

The PCI™ Local Bus Specification defines a number of power and reset requirements. When considered in an FPGA implementation, these create several challenges that must be addressed for long term reliability and broad interoperability. This application note applies to compliant PCI applications using Spartan™-3 Generation FPGAs, and is relevant to other Xilinx FPGA families, as well as related PCI applications.

The PCI specification defines two I/O timing budgets for use with 33 MHz and 66 MHz operation. In embedded designs, custom timing budgets enable the following: • Reduce total system cost by using less expensive devices • Achieve higher data transfer rates than allowed by specification • Add more loads to the bus to accommodate additional devices and connectors • Increase the physical length of the bus to accommodate novel bus topologies The information presented in this application note is applicable to any embedded PCI implementation using Xilinx FPGA devices.

This application note describes a DDR2 SDRAM memory interface implementation in a Spartan®-3 generation device, interfacing with a Micron DDR2 SDRAM device. This document provides a brief overview of the DDR2 SDRAM device features, followed by a detailed explanation of the DDR2 SDRAM memory interface implementation.

The Virtex™-II family of platform FPGAs has multipliers embedded into the FPGA fabric. These multipliers support several different multiplication modes of operation and can also function as barrel shifters.

This application note describes how memories wider than 36 bits can be efficiently implemented in the Virtex™-II and Spartan™-3 architectures. The clock-doubling method used is similar to the method described for quad-port memories in XAPP228. The resulting memories are used in either dual-port or single-port mode.

This application note describes how the existing dual-port block memories in the Spartan™-II and Virtex™ families can be used as Quad-Port memories. This essentially involves a data access time (halved) versus functionality (doubled) trade-off. The overall bandwidth of the block memory in terms of bits per second will remain the same.

When designing digital systems, there is often a requirement to synchronize incoming data and clock signals with an internal system clock (i.e., the internal and external clock are at exactly the same frequency, but due to variable backplane, board, or application-specific standard product (ASSP) delays, the phase relationship is not known). The circuit described in this application note addresses this issue for both single traces and data busses up to 160 MHz in a Virtex™-E, -7 device. The speed limitation is imposed by the maximum frequency that can be accepted by the Data Locked Loop (DLL), in a mode where it is capable of providing both a new clock and a new clock shifted by 90 degrees.

Data recovery is a mechanism that allows a receiver to extract embedded clock data from an incoming data stream. The receiver usually extracts this information from the data stream concerned, but sometimes the receiver’s clock is used for data transmission. The circuit described in this application note provides a partial solution at data rates up to 160 Mb/s in a Virtex™-E -7 device, a Spartan™-IIE -6 device, or a Spartan-3 -4 device, and up to 420Mb/s in a Virtex-II -5 device or a Virtex-II Pro™ -6 device. The solution is partial in the sense that no clock is actually recovered, but the data arriving is fully extracted. The speed is limited by the maximum frequency that can be accepted by the Delay Locked Loop (DLL), in a mode where the DLL is capable of providing both a new clock, and another clock shifted by 90 degrees.

Pseudo-random Noise (PN) generators are at the heart of every spread spectrum system. Many PN generators are required within Code Division Multiple Access (CDMA) base stations. PN generators are used to implement synchronization and uniquely code individual user signals across the transmission interface. PN generators are based upon Linear Feedback Shift Registers (LFSRs). Every Look-Up-Table (LUT) in a Virtex™ series or Virtex™-II series device can be configured as a 16-bit shift register (SRL16 macro). Hence, Virtex devices implement efficient LFSRs and deliver a significant reduction in resource utilization when compared with alternative flip-flop-only PLD structures.

Flexible CAMs (Content Addressable Memory) are implemented in Virtex™ devices by taking advantage of the reprogrammability of the basic LUT as a Shift Register or a SelectRAM™ memory and the fast carry logic chain. Although CAMs are also feasible in Spartan™ and XC4000X™ devices, this application note concentrates on Virtex devices.

This application note describes an approach to the 3.3V configuration of Spartan®-3 FPGAs. It provides a set of proven connection diagrams for each configuration mode. The same approach can be applied to the Spartan-3E family.

This application note provides a detailed description of the Spartan®-3 FPGA family configuration architecture. It explains the composition of the bitstream file and how this bitstream is interpreted by the configuration logic to program the part.

The block memories in the Virtex™-II architecture are capable of supporting data bus widths of up to 36-bits. A self-addressing FIFO reference design uses these block memories to store both data and address information in a single memory location. This application note describes FIFO designs where no external counters are required. Only flag and status information logic is used. The resulting FIFOs are not fast (around 150 MHz). Their advantage is in using only one clock load. In addition, the status mechanism is very simple making FIFOs are more suitable for data throttling in continuous data systems instead of the full or empty detection required in frame-based data systems.

This application note describes the implementation of 3 x 3 matrix multipliers in Virtex™-II devices. Many pipelined functions in the fields of computer graphics and video can be expressed in matrix mathematics. The example given here is color space conversion, which can be viewed as a subset of matrix multiplication. However, the technique can be extended to other matrix math functions as well.

The Digital Clock Manager (DCM) in the Virtex™-II series of FPGAs is an extremely powerful logic element. It allows fine phase adjustment of an incoming clock in increments of around 50 ps. This is typically necessary when clocking in an incoming data stream either single or double data rate at very high frequencies – up to 670 MHz SDR (420 MHz DDR) in a Virtex-II FPGA (-5 speed grade). Normally the DCM is set up to provide a constant phase shift that allows the incoming data to be correctly clocked in. This phase shift is corrected for both temperature and voltage, but can vary slightly across different devices and wafer lots, thus effectively reducing slightly the receiver window or "eye." One way of correcting for this is to set up the DCM phase shift dynamically via training either at device reset, or on a continuous basis. This concept forms the basis of this application note.

In data transmission systems, the transmission channel itself is a source of data error; consequently, there is a need to determine the validity of transmitted and received data. Parity generation and validation is a scheme to provide single bit error detection capabilities. This application note describes how to generate and validate parity in a design using the Virtex™-II architectural features including block RAM.

This application note describes techniques for remote reconfiguration of FPGAs through an Ethernet port.