Spartan/XL

Xilinx XC4000E/EX offer a wide variety of memory configuration options from Address and Data width to Dual-Port operation.

The Xilinx XC4000 Select-RAM memory offers the best size flexibility and at the same time offers high speed operation withvery little waste.

This application note provides users with a general understanding of the SVF and XSVF file formats as they apply to Xilinx devices. Some familiarity with IEEE STD 1149.1 (JTAG) is assumed. For information on using Serial Vector Format (SVF) and Xilinx Serial Vector Format (XSVF) files in embedded programming applications, refer to Xilinx Application Note XAPP058.

This application note discusses the configuration and programming options for Xilinx Complex Programmable Logic Device (CPLD), Field Programmable Gate Array (FPGA), and PROM families and demonstrates some of the most popular configuration methods used for each family. This document includes configuration quick start guidelines for the Virtex™, Spartan™, XPLA3, XC9500, and XC18V00 families.

This application note describes an interface between a video source and a PC. Note that this is a concept only - no design files were created. Although this targets the mature 5V Spartan FPGAs, the concepts are applicable to other products.

This application note illustrates the use of Spartan™ devices in an ADSL modem, for the complex system level glue logic required for the modem’s USB interface and for managing DMA transfers of ATM cells. The example shows how cost effective a Spartan device can be in these applications. It illustrates solutions to a number of general technical issues, including implementing Utopia interfaces for ATM devices and remote configuration of Spartan devices.

This application note illustrates the use of Spartan™ devices in an ISDN modem, showing how cost effective a Spartan device can be in these applications. While targeted at solving a specific problem, it illustrates solutions to a number of general technical issues.

This application note describes various methods to configure Spartan™ series FPGAs. Each configuration method is described in detail. Information on necessary software programs to run with input files required, output files produced, download cables used, and other hardware necessary to accomplish the task is discussed. This application note targets users who are new to Xilinx® devices and Alliance/Foundation series software tools and is intended to make the configuration and debugging flows easy to understand.

Power consumption plays an important role in battery-powered applications. Spartan™-XL FPGAs are designed with segmented routing, 3.3-V operation, and advanced process technology to meet the needs for low power and high performance. This application note shows how to reduce power consumption by selectively disabling portions of the design that are not required all the time. This approach is particularly useful for devices that must be operating at all times. This application note discusses different strategies for reducing the supply current incrementally for an operating device.

Spartan™-XL FPGAs come equipped with a Power Down mode that permits an exceptionally low level of power consumption (ICCO = 100 µA typical), making the family ideal for portable battery-powered applications. This application note provides all the information needed for a designer to use Power Down mode effectively, including descriptions of the mode's common applications, internal functioning and electrical characteristics.

The use of the internal IOB 3-state control register can significantly improve output enable and disable time. This application note illustrates the use of hard macros to implement this register in both HDL and schematic-based designs.

This application note provides information on how to perform Express configuration for the Spartan™-XL family. Express Mode uses an eight-bit-wide bus for fast configuration of Xilinx FPGAs. The steps of Express configuration are described, followed by detailed circuit implementation instructions.

This application note discusses the enormous strides made by Spartan™ series FPGAs in terms of density and performance and how it should be viewed as the Gate Array replacement. The Spartan device family offers many of the features that are desired by Gate Array designers with the major advantage of programmability, which can prove to be the key factor in the success of the product.

Spartan™ FPGAs are an exciting alternative for implementing digital designs that, previously, would have employed ASIC technology. Pre-existing ASIC intellectual property can be adapted for use with Spartan devices by following a straightforward procedure. Each step of the procedure is explained in detail. Guidelines show how an ASIC design, in the form of an RTL-level HDL file, can be revised to take full advantage of the Spartan series capabilities, thereby achieving efficient, high-performance implementations.

This application note describes how to achieve low-cost serial configuration for Spartan™/Spartan™-XL FPGA designs, including: taking advantage of unused resources in a design (thereby reducing cost), part count, memory size, and board space. The idle processing time of an on-board controller is used to load configuration data from an off-board source, which allows a Spartan design to be upgraded in the field by sending the bitstream over a network.

In the Spartan™ XC3000, XC4000, and XC5200 device families, Xilinx offers several evolutionary and compatible generations of Field Programmable Gate Arrays (FPGAs). This overview describes two aspects of Xilinx FPGAs: What logic resources are available to the user, and how the devices are programmed.

Xilinx FPGAs can be configured in a common daisy chain structure, where the lead device generates CCLK pulses and feeds serial configuration information into the next downstream device, which in turn feeds data into the next downstream device, etc. There is no limit to the number of devices in a daisy chain, and XC3000™, XC4000™, Spartan™, and XC5200™-series devices can be mixed freely with only one constraint: the lead device must be a member of the highest order family used in the chain.

These guidelines describe the configuration process for all members of the XC3000™, XC4000™, XC5200™, and Spartan™ FPGA devices and their derivatives. The average user need not understand or remember all these details, but should refer to the debugging hints when problems occur.

Data sheets describe I/O parameters in digital terms, providing tested and guaranteed worst-case values. This application note describes XC4000XL/XLA and Spartan™-XL I/O parameters in analog terms, giving the designer a better understanding of the circuit behavior. However, such parameters are not production-tested and are, therefore, not guaranteed.

All Xilinx FPGA families can be configured through a serial interface. This application note describes a simple, low-cost design to configure any Xilinx FPGA in a serial configuration mode using a Xilinx XC9500™ CPLD and any parallel PROM.

The XC4000E™/X and Spartan™ FPGA families provide distributed on-chip RAM. SelectRAM memory can be configured as level-sensitive or edge-triggered, single-port or dual-port RAM. The edge-triggered capability simplifies system timing and provides better performance for RAM-based designs. The dual-port mode offers new capabilities and simplifies FIFO designs.

XC4000™ and Spartan™ series FPGAs include SelectRAM memory, which can be configured as ROM or as single- or dual-port RAM, with edge-triggered or level-sensitive timing. This application note describes how to implement SelectRAM memory in a design: in schematic entry, using LogiBLOX synthesis, and HDL synthesis environments. Specifying timing requirements, evaluating performance, and floorplanning are also described.

This application note demonstrates the use of various RAM modes in XC4000™ and Spartan™ series logic blocks. A simple FIFO is implemented in several different ways, using combinations of level-sensitive (asynchronous) and edge-triggered (synchronous), single-port and dual-port RAM.

Shift registers longer than eight bits can be efficiently implemented in XC4000™ or Spartan™ series SelectRAM memory. Using Linear Feedback Shift Register (LFSR) counters to address the RAM makes the design even simpler. This application note describes 4- and 5-bit universal LFSR counters, very efficient RAM-based 32-bit and 100-bit shift registers, and pseudo-random sequence generators with repetition rates of thousands and even trillions of years, useful for testing and encryption purposes. The appropriate taps for maximum-length LFSR counters of up to 168 bits are listed.

This application note describes RAM-based FIFO designs using the dual-port RAM in XC4000™ Series devices. Synchronous designs with a common read/write clock are described, as well as asynchronous designs with independent read and write clocks. Emphasis is on the fast, efficient and reliable generation of the handshake signals FULL and EMPTY, which determine design performance.

This application note discusses various approaches available for implementing state machines in FPGA devices, in particular, the one-hot-encoding scheme for medium-sized state machines.

The XC4000/Spartan™ dedicated carry logic provides for very compact, high-performance counters. This application note describes a technique for increasing the performance of these counters using minimum additional logic. Using this technique, the counters remain loadable.

Using the XC4000™ or Spartan™ dedicated carry logic, the performance of adders and counters can easily be predicted. This application note provides formulae for estimating the performance of such adders and counters.

XC4000/XC5200/Spartan FPGA devices contain boundary scan facilities that are compatible with IEEE Standard 1149.1. This application note describes those facilities in detail, and explains how boundary scan is incorporated into an FPGA design.

This application note describes the XC4000/Spartan™ Readback capability and its use. Topics include: initialization of the Readback feature, format of the configuration and Readback bitstreams, timing considerations, software support for reading back FPGA devices, and Cyclic Redundancy Check (CRC).

This fully synchronous, non-loadable, binary counter uses a traditional prescaler technique to achieve high performance. Typically, the speed of a synchronous prescaler counter is limited by the delay incurred distributing the parallel Count Enable. This design minimizes that delay by replicating the LSB of the counter. In this way even the small longline delay is eliminated, resulting in the fastest possible synchronous counter.

This application note describes the operation of the XC4000/Spartan™ dedicated carry logic, the standard configurations provided for its use, and how these are combined into arithmetic functions and counters.

This paper discusses the overall purpose of OFFSET constraints, the specific paths that are covered by OFFSET constraints, and the differences between the OFFSET IN and OFFSET OUT constraints.

Surface Mount Technology (SMT) packages include the leaded family packages (Quad Flat Pack (QFP) and Plastic Leaded Chip Carrier (PLCC)) and the Ball Grid Array (BGA) packages. SMT rework can be necessary for any of the following reasons: assembly related defects, such as shorts, opens, wrong orientation, and solder ball defects; device/package related defects/failure analysis; and engineering change or system upgrade.

This white paper gives an overview of ISDN modem technologies and how Xilinx high volume programmable devices can be used to implement complex system level glue in ISDN modem designs.

This white paper gives an overview of digital modem technologies and how Xilinx high volume programmable devices can be used to implement complex system level glue in digital modem designs.

This white paper focuses on the market size for the various printer technologies, both by performance and geographic region. It then discusses the basics of the technologies, to give a view of their capabilities, limitations and future directions. It will then focus on exactly where Xilinx XC9500XL CPLDs and Spartan FPGAs play a vital role in this important market, then take a look into the future direction it is headed with Internet influence and the new photographic quality printers and MFPs.

This white paper describes a rarely noticed design technique that can make a difference in the size and the performance of your FPGA design. Control signals on FPGA flip-flops have a built-in priority. If you can learn to write code that is sympathetic to the priorities, the results will be rewarding. This white paper provides some simple VHDL and Verilog examples to explain key points.