Virtex-4

Even after volume shipments have begun, customers can take advantage of the "In-System ECO" (Engineering Change Orders) capability in Virtex™-4 EasyPath FPGAs to make changes to LUTs and I/Os. This application note describes how to make these changes in a simple way using the FPGA Editor tool.

This document provides an overview of all Xilinx memory interface application notes that support Virtex™ Series FPGAs. In addition, some key features of the prevalent memory technologies are also provided. For each application note, the data capture technique, clocking scheme, FPGA resources used, and supported memory technology are described briefly.

This application note describes a cost-optimized copy protection scheme that helps protect an FPGA against cloning. The design leverages an external secure serial EEPROM. The included reference design uses an optimized PicoBlaze™ 8-bit microcontroller. This application note provides a hardware design with associated PicoBlaze software code. The code loads a secret key into the secure EEPROM and authenticates the user system with the secure EEPROM.

This application note shows the connection of Xilinx® FPGAs to a Texas Instruments™ S320C6000 series Digital Signal Processor (DSP) using the available External Memory Interface (EMIF).

UltraController-II is a minimal footprint embedded processing engine based on the PowerPC™ 405 (PPC405) processor core embedded within Virtex™-4 and Virtex-II Pro Platform FPGAs. System designers can easily incorporate the UltraController-II black-box processing engine into larger ISE designs to gain additional degrees of freedom by balancing usage of the high-performance FPGA fabric with the algorithmic flexibility of software.

This application note explains how to use the Xilinx Viterbi Decoder LogiCORE™ module (version 5.0 or later) to implement both trellis termination and tail biting.

Describes how to implement a Virtex™-4 FX PowerPC™ 405 system with the Xilinx floating point unit (FPU) coprocessor.

This book-length compendium of Virtex™-II Pro and Virtex-4 audio and video connectivity solutions for the broadcast industry contains the latest updated revisions of previously-published serial video application notes, as well as new designs not previously released. See the Preface for a list of the original application note numbers this volume replaces.

This application note describes a reference design used to bridge one four-channel Xilinx SPI-4.2(PL4) core (v8.1) to four single-channel SPI-3 (PL3) Link Layer cores (v4.1), implemented in a single Virtex™-4 device.

This document contains detailed information related to the Virtex™-4 RocketIO™ Multi-Gigabit Transceiver (MGT) Static Operating Behavior described in EN014 (Errata for Virtex-4 FX CES2 and CES3 devices) and EN042 (Errata for Virtex-4 CES4 devices).

This application note describes a Redundant Array of Independent Disks (RAID) which is a hard-disk drive (HDD) array where part of the physical storage capacity stores redundant information. Data is regenerated from the physical storage if one or more of the disks in the array (including a single failed disk sector)or the access path to it fails.

This application note describes techniques for remote reconfiguration of FPGAs through an Ethernet port.

This application note details an embedded system example design of a web server running on a PowerPC™ core within a Xilinx Virtex™-4 FPGA. The system is designed using the Embedded Development Kit (EDK). The application note also explains how to set up a system as a web client and how to connect to the web server running on the PowerPC processor.

This application note details an embedded system example design of a Web server running on the MicroBlaze™ soft processor, designed using the Embedded Development Kit (EDK). The application note also explains how to set up a system as a Web client and how to connect to the Web server running on the MicroBlaze processor.

Hot-swapping or hot insertion describes a potentially dangerous method of inserting an unpowered board into a power-on (hot) running system. There are several concerns: the insertion must not cause physical harm or permanent damage to the system or the inserted board, and the insertion must not cause data corruption or any transient system upsets. This application note describes the physical aspects of hot-inserting a Virtex™-II based card into a system or system backplane, using sequenced connectors, where VCC and GND mate well before any signal pins can mate. The dangers of using normal non-sequenced connectors are described in Hot Plug-In. Not addressed in this application note are system issues including detecting the presence or absence of a card, or how the card is accepted in the system.

The OPB USB 2.0 Device core performs the functionality of a USB high speed device and is compliant with the USB 2.0 Specification.

This is a reference system for the OPB IIC on the ML402 Evaluation Platform.

This describes how to use Create IP Wizard to create custom IP and how to then use it in EDK.

This application note describes how to build a reference system using the OPB PCI Core on the ML410.

On-die termination (ODT) promises higher signaling rates for printed circuit board (PCB) inter-chip interfaces through improved signal integrity. However, when using ODT, there is sometimes an associated power penalty. This application note explains the reason for the power penalty and suggests a simulation technique for comparing the signal integrity and power dissipation of internally and externally terminated versions of an interface.

This application note describes a reference system illustrating how to build an embedded PowerPC™ system using the Virtex™-4 PLB Tri-Mode Ethernet Media Access Controller(PLB_TEMAC).

This application note discusses dynamic bus mode reconfiguration of PCI-X designs using LogiCORE™ solutions. It shows how to dynamically reload a Virtex™-4 and Virtex-5 FPGA after power-up using a CPLD to dynamically reconfigure the FPGA supporting PCI-X and PCI compatibility.

This application note focuses on the baseband demodulation of Quadrature Amplitude Modulation (QAM) signals and, more specifically, on the use of a fractional rate decimator block. This application note also reviews polyphase decimating filter architectures and discusses the fractional rate decimator, its Xilinx System Generator 8.1i implementation, and its results.

This application note provides information on using the PLB DDR2 with OPB Central DMA.

This application note provides a Xilinx FPGA solution to two-dimensional filtering with a parameterized VHDL reference design.

This application note describes the implementation of six circuits necessary to perform commonly used conversions between various chroma formats.

This document presents design techniques and reference circuits that power Virtex™-4 FX RocketIO™ multi-gigabit transceivers (MGTs) operating at data rates below 3.125 Gb/s.

This application note shows how the 32-bit MicroBlaze™ processor can easily access wide data width memories. The design is also suitable for use with the IBM PowerPC™ (PPC405) processor because it connects to the On-chip Peripheral Bus (OPB). The reference design provides a modification to an existing Xilinx EDK SDRAM interface, enabling a 32-bit processor to access a 64-bit data bus.

Provides an overview of the baseband processing of a typical W-CDMA base station, along with the associated implementation challenges faced by W-CDMA equipment manufacturers, including the silicon cost, flexibility, and scalability trade-offs.