Virtex-5 White Papers

This white paper updates the results from the 2005 Xilinx Rosetta experiments published in IEEE Transactions on Device and Materials Reliability, clarifies some open issues, and presents additional results for 90 nm and 65 nm technology nodes.

This white paper describes a rarely noticed design technique that can make a difference in the size and the performance of your FPGA design. Control signals on FPGA flip-flops have a built-in priority. If you can learn to write code that is sympathetic to the priorities, the results will be rewarding. This white paper provides some simple VHDL and Verilog examples to explain key points.

This white paper gives an overall view of the various mainstream digital television standards and outlines related Forward Error Correction solutions available from Xilinx for cable, satellite, terrestrial, and mobile systems.

This white paper discusses chip multiprocessing designs using the Xilinx Platform Studio

The innovative Virtex™-5 architecture, which is based on a real 6-input LUT with dual-LUT capability, provides substantial resource utilization advantages over competing architectures. This white paper details these advantages.

This white paper reviews the potential inaccuracies associated with the traditional one-resistor approach to selecting heatsinks, and suggests a more accurate two-resistor (2-R) approach based on both theta-jc and theta-jb from the device datasheet.

This paper focuses on how Xilinx Platform Flash PROMs simplify FPGA configuration design for system and board designers.

This white paper provides a high-level explanation of the inherent and standards-fulfilling security features of the Xilinx Virtex™-4 and Virtex-5 FPGA families that have earned the trust of both government and commercial institutions.

This white paper addresses power consumption in 65 nm FPGAs.

This white paper discusses the various memory interface controller design challenges and Xilinx solutions, including how to use the Xilinx software tools and hardware-verified reference designs to build a complete memory interface solution for your own application, from low-cost DDR SDRAM applications to higher-performance interfaces like the 667Mb/s DDR2 SDRAMs.

This document shows the level of performance that can be reached with Virtex™-5 family building blocks, with particular emphasis on the new ExpressFabric™ technology. The main features of this new technology, including the new 6-input LUT, are described.

When migrating or retargeting code from a previous design into a Virtex™-5 platform FPGA, some considerations should be addressed. This whitepaper identifies and details appropriate retargeting guidelines.

This white paper discusses some of the advantages made available to the application design engineer by the Virtex™-5 family’s advanced approach to FPGA packaging.

This white paper offers design tips on changes that can be made to the FPGA environment, features, and tool options to optimize the system design power consumption, thus reducing thermal and power component cost as well as increasing overall system reliability.

This white paper covers the different kinds of IIR filters and structures, and, with the use of The MathWorks® tools, shows how these structures can be mapped to the Xilinx® FPGA architecture.

This white paper explores solutions for implementing FIFOs in Virtex™-5 FPGAs.

This white paper examines the causes of jitter, jitter measurement techniques, and methods of managing jitter in digital systems.

This white paper discusses signal analysis requirements and methods for printed circuit board design for Xilinx® FPGAs.

This white paper defines IBIS models and describes how to use them to model I/O characteristics for Xilinx® FPGAs.

This white paper defines the use and limitations of bit error ratio measurements when analyzing the performance of communications links.

This white paper describes design techniques that improve signal integrity in Xilinx® FPGAs.

This white paper examines alternate uses of available block RAM in Virtex® and Spartan® FPGAs.

This white paper examines how to remove the DC content from a digitally sampled waveform using DSP without complicated mathematics.

This white paper explores the factors of PCI Express® technology and how they affect the performance of a system. This document also provides performance results from two systems that use the Xilinx® Endpoint Block Plus Wrapper for PCI Express in the Virtex®-5 FPGA Integrated Endpoint Block for PCI Express designs.

This white paper examines the industry's urgent need for higher rate interfaces (particularly 100 GbE), the important risks and concerns that a system architect has when adding 100 GbE to a platform, and several implementation options that show how FPGAs are uniquely positioned to handle these challenges.

This white paper describes the steps necessary to analyze your design's power requirements using the Xilinx® Power Estimator.