Virtex-II

This application note describes the implementation of a two-dimensional Rank Order filter. The reference design includes the RTL VHDL implementation of an efficient sorting algorithm.

This application note provides a Xilinx FPGA solution to two-dimensional filtering with a parameterized VHDL reference design.

This application note describes the implementation of six circuits necessary to perform commonly used conversions between various chroma formats.

This application note describes the implementation of a YCrCb color space to an RGB Color space conversion circuit necessary in many video designs.

This application note describes the implementation of an RGB color space to a YCbCr color space conversion circuit necessary in many video designs.

This application note discusses the use of Partitions in the Incremental Design Flow. It is recommended that module instances with high logic density, timing critical paths, or timing critical module instances be designated Partitions.

This document provides an overview of all Xilinx memory interface application notes that support Virtex™ Series FPGAs. In addition, some key features of the prevalent memory technologies are also provided. For each application note, the data capture technique, clocking scheme, FPGA resources used, and supported memory technology are described briefly.

This application note describes a cost-optimized copy protection scheme that helps protect an FPGA against cloning. The design leverages an external secure serial EEPROM. The included reference design uses an optimized PicoBlaze™ 8-bit microcontroller. This application note provides a hardware design with associated PicoBlaze software code. The code loads a secret key into the secure EEPROM and authenticates the user system with the secure EEPROM.

This application note describes the use of partial reconfiguration in Virtex™-II series FPGAs for the purpose of correcting Single Event Upsets to the configuration memory array induced by cosmic rays. It is essential for the reader to have a basic understanding of the Virtex™-II SelectMAP interface as well as configuration and readback operations.

This application note describes the 10 Gigabit Ethernet Physical Coding Sublayer (PCS) reference design for Xilinx Virtex-II™ and Virtex-II Pro™ FPGAs. The PCS connects between a Xilinx RocketPHY™ 10 Gb/s transceiver and the Xilinx LogicCORE™ 10 Gigabit Ethernet Media Access Controller (MAC) core, LogicCORE XAUI core or 10 Gigabit Media Independent Interface (XGMII) Reference Design (XAPP606).

This application note describes how to connect a high-speed Texas Instruments (TI) ADS5273 analog-to-digital converter (ADC) with serialized LVDS output to a Virtex™-II or Virtex™-II Pro FPGA. Lower speed ADC devices from this family can be connected to Spartan™-3 FPGAs.

This application note shows how a designer can very simply implement a battery with the Virtex-II™ series FPGAs for high bitstream security. It shows a number of Xilinx recommended designs.

This application note shows how a Xilinx Virtex-II™ or Virtex-II Pro™ device can connect to a Philips TZA3015HW 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver. The reference design with this application note uses the TZA3015HW.

This application note shows the connection of Xilinx® FPGAs to a Texas Instruments™ S320C6000 series Digital Signal Processor (DSP) using the available External Memory Interface (EMIF).

This application note and its accompanying reference design describe a dynamic phase alignment (DPA) module used in bus interfaces, such as SPI 4.2, using asynchronous data capture techniques. The DPA module can run at 800 Mbps and faster in Virtex-II™ and Virtex-II Pro™ devices. It contains a word-alignment unit that can remove channel-to-channel skew. This document is an extension of XAPP671: High-Speed Data Recovery Using Asynchronous Data Capture Techniques.

This application note describes how to retrieve user-defined data from Xilinx configuration PROMs (XC18V00 and Platform Flash devices) after the same PROM has configured the FPGA. The method to add user-defined data to the configuration PROM file is also discussed.

This application note illustrates the use of a Xilinx CoolRunner-II™ CPLD to monitor configuration data between a Xilinx Platform Flash Configuration PROM and a Xilinx Spartan™ or Virtex™ family FPGA. The intent is to ensure reliable configuration of the FPGA while providing revision control for one or more configuration files stored in the PROM.

The Reduced Gigabit Media Independent Interface (RGMII) is an alternative to the Gigabit Media Independent Interface (GMII). In this application note, an RGMII adaptation module is used to reduce the number of pins required to connect the Gigabit Ethernet MAC to a Gigabit PHY from 24 to 12.

This application note describes the implementation of a parameterizable LocalLink FIFO, which is a First-In-First-Out memory queue with LocalLink interfaces on both sides. The LocalLink interface defines a set of protocol-agnostic signals that allows transmission of packet-oriented data, and enables a set of features such as flow control and transfer data of arbitrary length. The LocalLink FIFO consists of two LocalLink interfaces, one on the write port to interface with an upstream user application, the other on the read port to interface with a downstream user application.

This application note describes how block memories efficiently can implement a serializer or a deserializer function or both with or without pattern-matching capabilities in the Virtex™-II, Virtex-II Pro™, and Spartan™-3 architectures.

Ground bounce must be controlled to ensure proper operation of high performance FPGA devices. Particular attention must be applied to minimizing board-level inductance during PCB layout. This document describes calculations that help to ensure that a design meets input undershoot and logic-low voltage requirements for devices receiving signals from an FPGA.

This application note describes the encoding and decoding blocks of the 64B/66B encoding scheme. This application allows designs to use the RocketIO transceiver of the Virtex-II Pro™ device or an external SERDES with either Virtex-II or Virtex-II Pro devices.

This application note describes using asynchronous data capture techniques as a method for high-speed data recovery in Virtex™-II and Virtex-II Pro™ devices. The reference designs accompanying this application note show how data is recovered in an interface running at 622 Mb/s DDR with 0.3UI of jitter.

This application note describes the logic to perform basic word alignment and deframing specifically for SONET/SDH systems, where data is being processed at 16-bits or 64-bits per clock cycle.

This application note examines the design of scramblers for use with Synchronous Optical NETworks (SONET) and Optical Transport Network (OTN) designs using the Virtex™ series of FPGAs. The scrambler function for Synchronous Digital Hierarchy (SDH) is the same as that for SONET.

This application note describes how to connect Virtex™-II, Virtex-II Pro, Virtex-4, Virtex-5, Spartan™-3, and Spartan-3E devices to 3.3V or 5V PCI buses. The design responds to customer demand for a general solution for applications with a Virtex-II device and a 5V PCI bus, as well as for applications with a Virtex-II Pro, Virtex-4, Virtex-5, Spartan-3, or Spartan-3E device and a 3.3V or 5V PCI bus.

This application note describes the implementation of an Error Correction Control (ECC) module in a Virtex™-II, Virtex-II Pro, Virtex-4, and Virtex-5 device. The design can detect and correct all single bit errors (in a code word consisting of either 64-bit data and 8 parity bits, or 32-bit data and 7 parity bits), and it can detect double bit errors in the data. This design utilizes Hamming code, a simple yet powerful method for ECC operations. As a result, this design offers exceptional performance and resource utilization.

HyperTransport is a high-speed bus designed to move data from processors to peripherals at speeds up to 60 times faster than a 32-bit PCI bus operating at 66 MHz. The HyperTransport bus provides this performance enhancement while remaining compatible with PCI. A minimal version of the HyperTransport protocol called HyperTransport Lite has been developed and is described in this application note. The reference design is implemented in a Virtex™-II device and can run at a frequency of up to 400 MHz.

This application note describes a high-speed, optimized implementation of a Virtex-II™ pipelined multiplier primitive (MULT18X18 and MULT18X18S) implemented in VHDL and Verilog.

This application note describes a transmitter module and a receiver module compatible with Analog Devices TigerSHARC TS20x digital signal processors (DSPs). These two macros allow double data-rate (DDR) communication of 128-bit words over a four-bit LVDS link at speeds up to 1000 Mb/s per line (500 MB/s) when a Virtex-II™ Pro grade -7 device is transmitting, and up to 500 Mb/s per line when a Virtex-II Pro grade -7 device is receiving.

This application note describes a full-featured transmitter/receiver macro that can communicate with Spartan™ and Virtex™ FPGA families via the Analog Devices ADSP-TS101S TigerSHARC™ link-port function.

The Virtex™-II series of FPGAs provide access and interface to a variety of memory resources, both off and on the FPGA. In addition to the on-chip distributed RAM and block RAM features, Virtex-II FPGAs interface to a variety of external high-speed memory devices. One such device is the new Multi-Queue™ FIFO family, a powerful new memory architecture manufactured by Integrated Device Technology (IDT™).

The Virtex™-II series of FPGAs provide access and interface to a variety of on-chip and off-chip devices. In addition to the on-chip distributed RAM and block RAM features, Virtex-II FPGAs can interface to a variety of external high-speed memory devices. The combination of the high-speed selectable I/O resources and on-chip Digital Clock Manager (DCM) circuits enable a high-bandwidth interface to a high-speed, high-density FIFO. This application note presents an overview of a general interface between an IDT TeraSync™ FIFO and the Virtex-II FPGA.

The PicoBlaze™ module is a fully embedded 8-bit microcontroller macro for the Virtex™-II series. Although it could be used for processing of data, the PicoBlaze™ macro is most likely to be employed in applications requiring a complex, but non-time-critical state machine.

This application note describes the design of an interface between a Xilinx Virtex™-II FPGA and a Velio Communications SerDes device. The reference design specifically uses a Velio VC1003 and a Xilinx XC2V1000 FPGA.

This application note covers the principles of power distribution systems and bypass or decoupling capacitors. A step-by-step process is described where a power distribution system can be designed and verified. The final section discusses additional sources of power supply noise and provides resolutions.

This application note describes single data rate (SDR) transmitter and receiver interfaces operating at up to 644 MHz, using 17 Low-Voltage Differential Signaling (LVDS) pairs (one clock and 16 data channels). The design can be implemented in both Virtex-II™ and Virtex-II Pro™ FPGAs. The accompanying reference design files include an example implementation targeting a Virtex-II XC2V3000FF1152 -5 speed grade device.

This application note describes the implementation of Variable Length Coding (VLC) on Xilinx devices. Zig-zag coding and run length coding are done in an MPEG-2 encoder. The zig-zag coding arranges the DCT coefficients in the order of increasing frequency. These coefficients are then coded as a run-length pair where the run is the number of occurrences of a value and the length is the amplitude.

This application note describes the different local clocking resources available in the Virtex™-II architecture. Along with a reference design, the document details how to use the local clocking resources in source-synchronous applications.

This application note shows how to interface an external high-speed serial communications device to a Xilinx Virtex™-II FPGA. It also shows how the hardware inside the FPGA can be designed by means of a working example.

The Cyclic Redundancy Check (CRC) is a powerful technique to obtain data reliability. This application note discusses the implementation of Configurable CRC Modules with LocalLink interfaces. The user can tailor the features of these modules to suit the protocol or application that is implemented in their system. The user-specified options for each of the configurable features are input parameters to the VHDL code for the modules.

This application note explains how to use the Xilinx Viterbi Decoder LogiCORE™ module (version 5.0 or later) to implement both trellis termination and tail biting.

MicroBlaze™ has the ability to use its dedicated FSL bus interface to integrate a customized IP core into a MicroBlaze soft processor-based system. This document describes possible methods to include customized IP cores into an SCP-based design.

This application note describes a reference design used to bridge one 4-channel Xilinx SPI-4.2 (PL4) Core to four 1-channel SPI-3 (PL3) Link Layer Cores. The design is implemented in a Virtex™-II device.

This book-length compendium of Virtex™-II Pro and Virtex-4 audio and video connectivity solutions for the broadcast industry contains the latest updated revisions of previously-published serial video application notes, as well as new designs not previously released. See the Preface for a list of the original application note numbers this volume replaces.

This application note discusses the configuration and programming options for Xilinx Complex Programmable Logic Device (CPLD), Field Programmable Gate Array (FPGA), and PROM families and demonstrates some of the most popular configuration methods used for each family. This document includes configuration quick start guidelines for the Virtex™, Spartan™, XPLA3, XC9500, and XC18V00 families.