Virtex-II Pro

The oversampling module described in this application note performs 3/4/5/6X oversampling. The oversampling ratio is selectable during operation to facilitate multi-rate applications. It is designed to accept 20 bits of oversampled data and to output 10 bits of extracted data to the user interface. This module can be used with the Virtex-II Pro™ RocketIO™ Multi-Gigabit Transceiver (MGT) to achieve line rates of 200 Mb/s to 1000 Mb/s.

This document provides an overview of all Xilinx memory interface application notes that support Virtex™ Series FPGAs. In addition, some key features of the prevalent memory technologies are also provided. For each application note, the data capture technique, clocking scheme, FPGA resources used, and supported memory technology are described briefly.

This application note describes a cost-optimized copy protection scheme that helps protect an FPGA against cloning. The design leverages an external secure serial EEPROM. The included reference design uses an optimized PicoBlaze™ 8-bit microcontroller. This application note provides a hardware design with associated PicoBlaze software code. The code loads a secret key into the secure EEPROM and authenticates the user system with the secure EEPROM.

The design described in this application note utilizes the Virtex-II Pro™ RocketIO™ transceivers, the Xilinx Aurora Protocol Engine, and the 1-Gigabit Ethernet MAC core to provide a bridge between Aurora and Gigabit Ethernet. In addition, it can act as a starting point for systems wishing to use either Gigabit Ethernet or Aurora for general data transfer. Target applications include connecting Aurora devices to legacy Gigabit Ethernet networks, testing Aurora devices using Gigabit Ethernet traffic, and building larger systems requiring Aurora or Gigabit Ethernet interfa

This application note describes a method for bypassing the AC coupling in Virtex™-II Pro X devices. Doing so allows use of the 10 Gb/s RocketIO™ Multi-Gigabit Transceiver (MGT) in DC-coupled over-sampling applications.

This application note describes the 10 Gigabit Ethernet Physical Coding Sublayer (PCS) reference design for Xilinx Virtex-II™ and Virtex-II Pro™ FPGAs. The PCS connects between a Xilinx RocketPHY™ 10 Gb/s transceiver and the Xilinx LogicCORE™ 10 Gigabit Ethernet Media Access Controller (MAC) core, LogicCORE XAUI core or 10 Gigabit Media Independent Interface (XGMII) Reference Design (XAPP606).

This application note describes how to connect a high-speed Texas Instruments (TI) ADS5273 analog-to-digital converter (ADC) with serialized LVDS output to a Virtex™-II or Virtex™-II Pro FPGA. Lower speed ADC devices from this family can be connected to Spartan™-3 FPGAs.

This application note describes how to use a Virtex™-II Pro device to interface to Common I/O (CIO) Double Data Rate (DDR) Reduced Latency DRAM (RLDRAM II) devices. The reference design targets two CIO DDR RLDRAM II devices at a clock rate of 270 MHz with data transfers at 540 Mb/s per pin.

This application note shows how a designer can very simply implement a battery with the Virtex-II™ series FPGAs for high bitstream security. It shows a number of Xilinx recommended designs.

This application note shows how a Xilinx Virtex-II™ or Virtex-II Pro™ device can connect to a Philips TZA3015HW 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver. The reference design with this application note uses the TZA3015HW.

This application note describes the local clocking resources available in the Virtex-II Pro™ architecture for the RXRECCLK of the 3.125 Gb/s RocketIO™ MGTs.

This application note describes the implementation of a RocketIO X™ bit-error rate tester (XBERT) reference design. The reference design generates and verifies non-encoded high speed serial data on one or multiple point-to-point links (2.5 Gb/s to 10 Gb/s) between RocketIO X multi-gigabit transceiver (MGT) ports, embedded within a single Virtex-II Pro X FPGA.

This application note describes a Configurable Physical Coding Sublayer (CPCS) reference design that extends the functionality of the Xilinx RocketIO™ multi-gigabit transceiver (MGT) blocks in the Virtex™-II Pro FPGA family.

The serial transfer of data between devices on a board or cards on a backplane using the LVDS differential standard is well established. Existing cards need to be able to interface to newer technologies. This application note discusses two possible ways to interconnect standard LVDS transceivers with the Current Mode Logic (CML) technology used in Xilinx RocketIO™ multi-gigabit transceivers (MGTs) through AC coupling and DC coupling.

The embedded PowerPC™ 405 processor blocks in Virtex-II Pro™ devices with –7 speed grades can achieve speeds to 400 MHz. Special considerations are necessary when using the left processor in dual-processor devices. This application note describes these considerations and provides a necessary macro when operating the left processor at speeds greater than 350 MHz.

This application note shows the connection of Xilinx® FPGAs to a Texas Instruments™ S320C6000 series Digital Signal Processor (DSP) using the available External Memory Interface (EMIF).

Huffman coding is used to code values statistically according to their probability of occurence. Short code words are assigned to highly probable values and long code words to less probable values. Huffman coding is used in MPEG-2 to further compress the bitstream. This application note describes how Huffman coding is done in MPEG-2 and its implementation.

This application note describes a reference design to do a quantization and inverse quantization of MPEG-2 video signals. After a brief introduction, the process of using JPEG and MPEG-2 standards for quantizing matrices is developed. Finally, implementing the Xilinx solution for quantization or inverse quantization is described.

This application note describes a two-dimensional Inverse Discrete Cosine Transform (2D IDCT) function implemented on a Xilinx FPGA. The reference design file provides behavioral code for implementation on any Xilinx device.

This application note describes the different local clocking resources available in the Virtex™-II architecture. Along with a reference design, the document details how to use the local clocking resources in source-synchronous applications.

This application note describes a 3X-oversampling reference design that provides a 200 Mb/s to 1000 Mb/s serial interface using the Virtex™-II Pro RocketIO™ multi-gigabit transceiver (MGT). The reference design implements a 3X-oversampling circuit at the back end of the MGT and is targeted for the Fibre Channel rate of 1.0625 Gb/s.

UltraController-II is a minimal footprint embedded processing engine based on the PowerPC™ 405 (PPC405) processor core embedded within Virtex™-4 and Virtex-II Pro Platform FPGAs. System designers can easily incorporate the UltraController-II black-box processing engine into larger ISE designs to gain additional degrees of freedom by balancing usage of the high-performance FPGA fabric with the algorithmic flexibility of software.

The DEBUGHALT controller is a small, yet versatile piece of FPGA logic that simplifies the startup process of the PowerPC™ 405 (PPC405) processors in systems that cannot have any memory at the reset vector, or in systems that completely run out of cache. This application note is accompanied by a reference design that demonstrates debug halt mode implemented in the embedded PPC405 processor available on Virtex-II Pro™ FPGAs. The DEBUGHALT controller design enables external control of the PPC405 processor through the JTAG interfa

This application note describes the implementation of a processor lockstep system using embedded PowerPC™ 405 (PPC405) processors in Xilinx Virtex™-II Pro FPGAs, along with Xilinx software tools. To verify lockstep functionality, users learn how to build and run the Linux operating system with the MontaVista Linux Preview Kit and also how to probe signals in the lockstep system with Xilinx ChipScope™ Pro tools.

The Cyclic Redundancy Check (CRC) is a powerful technique to obtain data reliability. This application note discusses the implementation of Configurable CRC Modules with LocalLink interfaces. The user can tailor the features of these modules to suit the protocol or application that is implemented in their system. The user-specified options for each of the configurable features are input parameters to the VHDL code for the modules.

This application note explains how to use the Xilinx Viterbi Decoder LogiCORE™ module (version 5.0 or later) to implement both trellis termination and tail biting.

This application note describes a DDR2 SDRAM memory interface for Virtex™-II Pro FPGAs.

This document describes how to get started using the Treck TCP/IP stack and Xilinx EDK tools. An evaluation version of the Treck TCP/IP stack is included as part of the application note. An example TCP application uses the Treck TCP/IP stack to send TCP data over Gigabit Ethernet on the Virtex-II Pro ™ ML300 Development Board to a remote PC-based server.

This application note describes how to generate statistical profiling information from the IBM PowerPC 405D, which is embedded in some Virtex-II Pro™ FPGAs. Specifically, the application note details how to convert trace output files generated from the Agilent Technologies Trace Port Analyzer into a gprof (GNU profiler) readable format. The gprof tool is capable of generating a histogram of a program's functions and a call-graph table of those functions.

This application note covers the steps necessary to run the open source firmware, Universal Bootloader (U-Boot), and to use it to boot Linux on the embedded IBM PowerPC™ 405 (PPC405) processor available on Virtex-II Pro™ ML300 Evaluation Platforms.

This application note describes the implementation of a traffic groomer that bridges the system space between a network line port (in this case, Gigabit Ethernet frame traffic) and the Mesh Fabric Reference Design (MFRD).

This application note describes an embedded Simple Mail Transfer Protocol (SMTP) client reference design that demonstrates the capacity of a network-enabled embedded system to report on its status via E-mail. It describes how to set up the Platform Studio design environment for the PowerPC™ 405, configure the 10/100 Ethernet MAC core, and create the Board Support Package (BSP) for VxWorks®.

Today's serial backplane implementations support line rates ranging from 622 Mbps to 3.125 Gbps and are now approaching speeds in excess of 10 Gbps. A significant recent development is the emergence of standards to define serial backplanes. Whether proprietary or standards-based, serial backplanes present a very demanding signaling environment with high signal density, multiple connectors, and substantial trace lengths. Proving and characterizing the performance of any high-speed serial solution is critical, and MultiBERT provides a means of accomplishing this with Xilinx™ Multi-Gigabit Transceivers (MGTs).

The Gigabit System Reference Design (GSRD) leverages the techniques outlined in Xilinx application note XAPP535 to demonstrate a high-performance Gigabit Ethernet reference system using a Xilinx Virtex-II Pro FPGA.

This application note introduces two key technologies from the Gigabit System Reference Design (GSRD): the Multi-Port Memory Controller (MPMC), which allows multiple entities to directly access memory bypassing a system bus, and the Communication Direct Memory Access Controller (CDMAC), which works with the MPMC to provide multiple channels of Direct Memory Access (DMA) for communication style devices.

MicroBlaze™ has the ability to use its dedicated FSL bus interface to integrate a customized IP core into a MicroBlaze soft processor-based system. This document describes possible methods to include customized IP cores into an SCP-based design.

This application note describes a reference design used to bridge one 4-channel Xilinx SPI-4.2 (PL4) Core to four 1-channel SPI-3 (PL3) Link Layer Cores. The design is implemented in a Virtex™-II device.

This book-length compendium of Virtex™-II Pro and Virtex-4 audio and video connectivity solutions for the broadcast industry contains the latest updated revisions of previously-published serial video application notes, as well as new designs not previously released. See the Preface for a list of the original application note numbers this volume replaces.

This application note describes a 200 MHz four-word burst QDR II SRAM interface implemented in a Virtex-II Pro™ XC2VP20 FF1152 –6 device.

The Queue Manager Reference Design (QMRD) illustrates per-flow queuing for network processing applications, along with class-based flow control. The QMRD segments variable length frames into fixed length Fabric Protocol Data Units (PDUs) when configured for ingress queuing, and reassembles fixed length Fabric PDUs into variable length frames when configured for egress queuing. It provides command and status interfaces that can be connected to a traffic scheduler, providing a complete traffic queuing and scheduling solution.

Describes a working Virtex™-II Pro PowerPC™ system that uses the Dhrystone benchmark and the reference design on which the system runs.